DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 340

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 13 I
Rev. 2.00 Mar 21, 2006 page 300 of 518
REJ09B0299-0200
Figure 13.7 Sample Flowchart for Operations in Master Transmit Mode
2
C Bus Interface (IIC)
No
No
No
No
No
Write transmit data in ICDR
Write transmit data in ICDR
Read BBSY flag in ICCR
Read IRIC flag in ICCR
Read ACKB bit in ICSR
Read IRIC flag in ICCR
Read ACKB bit in ICSR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Yes
Set BBSY =1 and
Set BBSY = 0 and
Set MST = 1 and
End of transmission?
TRS = 1 in ICCR
SCP = 0 in ICCR
SCP = 0 in ICCR
Transmit mode?
Initialize IIC
ACKB = 0?
or ACKB = 1?
BBSY = 0?
IRIC = 1?
IRIC = 1?
IRIC = 1?
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
No
No
[1] Initialization
[2] Test the status of the SCL and SDA lines.
[3] Select master transmit mode.
[4] Start condition issuance
[5] Wait for a start condition generation
[6] Set transmit data for the first byte
[7] Wait for 1 byte to be transmitted.
[8] Test the acknowledge bit
[9] Set transmit data for the second and
[10] Wait for 1 byte to be transmitted.
[11] Determine end of tranfer
[12] Stop condition issuance
(slave address + R/W).
(After writing to ICDR, clear IRIC flag
continuously.)
transferred from the slave device.
subsequent bytes.
continuously.)
(After writing to ICDR, clear IRIC flag
Master receive mode