DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 396

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 14 Keyboard Buffer Controller
14.5
14.5.1
When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the
KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the
KCLK falling edge is detected.
If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 14.14 shows the
timing of KBIOE setting and KCLK falling edge detection.
14.5.2
Keyboard buffer controller operation can be enabled or disabled using the module stop control
register. The initial setting is for keyboard buffer controller operation to be halted. Register access
is enabled by canceling module stop mode. For details, refer to section 19, Power-Down Modes.
Rev. 2.00 Mar 21, 2006 page 356 of 518
REJ09B0299-0200
φ
KCLK (pin)
Internal KCLK
(KCLKI)
KBIOE
Falling edge
signal
KBFSEL
KBE
KBF
Usage Notes
KBIOE Setting and KCLK Falling Edge Detection
Module Stop Mode Setting
Figure 14.14 KBIOE Setting and KCLK Falling Edge Detection Timing
T
1
T
2