DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 421

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

15.3.8
The SIRQCR registers contain status bits that indicate the SERIRQ operating mode and bits that
specify SERIRQ interrupt sources.
Bit
7
6
5
SIRQCR0
Bit Name Initial Value Slave Host Description
Q/C
SELREQ 0
IEDIR
SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1)
0
0
R
R/W
R/W
R/W
—
—
—
Quiet/Continuous Mode Flag
Indicates the mode specified by the host at the end
of an SERIRQ transfer cycle (stop frame).
0: Continuous mode
[Clearing conditions]
1: Quiet mode
[Setting condition]
Specification by SERIRQ transfer cycle stop frame.
Start Frame Initiation Request Select
Selects whether start frame initiation is requested
when one or more interrupt requests are cleared, or
when all interrupt requests are cleared, in quiet
mode.
0: Start frame initiation is requested when all
interrupt requests are cleared in quiet mode.
1: Start frame initiation is requested when one or
more interrupt requests are cleared in quiet mode.
Interrupt Enable Direct Mode
Specifies whether LPC channel 2 and channel 3
SERIRQ interrupt source (SMI, IRQ6, IRQ9 to
IRQ11) generation is conditional upon OBF, or is
controlled only by the host interrupt enable bit.
0: Host interrupt is requested when host interrupt
enable bit and corresponding OBF are both set to 1
1: Host interrupt is requested when host interrupt
enable bit is set to 1
LPC hardware reset, LPC software reset
Specification by SERIRQ transfer cycle stop
frame
Section 15 Host Interface LPC Interface (LPC)
Rev. 2.00 Mar 21, 2006 page 381 of 518
REJ09B0299-0200