UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 1008

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UPD78F1000GB-GAF-AX

Manufacturer Part Number
UPD78F1000GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet

Specifications of UPD78F1000GB-GAF-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1000GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
78K0R/Kx3-L
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Instruction
8-bit data
transfer
16-bit
data
transfer
Group
2.
3.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
Mnemonic
XCH
ONEB
CLRB
MOVS
MOVW
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
When the program memory area is accessed.
Except rp = AX
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
register (CKC).
A, ES:!addr16
A, ES:[DE]
A, ES:[DE + byte]
A, ES:[HL]
A, ES:[HL + byte]
A, ES:[HL + B]
A, ES:[HL + C]
A
X
B
C
saddr
!addr16
ES:!addr16
A
X
B
C
saddr
!addr16
ES:!addr16
[HL + byte], X
ES:[HL + byte], X
rp, #word
saddrp, #word
sfrp, #word
AX, saddrp
saddrp, AX
AX, sfrp
sfrp, AX
AX, rp
rp, AX
Operands
Note 3
Note 3
Bytes
Table 29-5. Operation List (4/17)
5
3
4
3
4
3
3
1
1
1
1
2
3
4
1
1
1
1
2
3
4
3
4
3
4
4
2
2
2
2
1
1
Note 1 Note 2
3
3
3
3
3
3
3
1
1
1
1
1
1
2
1
1
1
1
1
1
2
1
2
1
1
1
1
1
1
1
1
1
Clocks
A ←→ (ES, addr16)
A ←→ (ES, DE)
A ←→ ((ES, DE) + byte)
A ←→ (ES, HL)
A ←→ ((ES, HL) + byte)
A ←→ ((ES, HL) + B)
A ←→ ((ES, HL) + C)
A ← 01H
X ← 01H
B ← 01H
C ← 01H
(saddr) ← 01H
(addr16) ← 01H
(ES, addr16) ← 01H
A ← 00H
X ← 00H
B ← 00H
C ← 00H
(saddr) ← 00H
(addr16) ← 00H
(ES,addr16) ← 00H
(HL + byte) ← X
(ES, HL + byte) ← X
rp ← word
(saddrp) ← word
sfrp ← word
AX ← (saddrp)
(saddrp) ← AX
AX ← sfrp
sfrp ← AX
AX ← rp
rp ← AX
CPU
) selected by the system clock control
Operation
CHAPTER 29 INSTRUCTION SET
Z AC CY
×
×
Flag
×
×
1008

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