UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 482

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
8.8.3 Operation as multiple PWM output function
can be output.
following expressions.
waveform from the TOmp pin. The TCRmp register loads the value of timer data register mp (TDRmp), using INTTMmn of
the master channel as a start trigger, and starts counting down. When TCRmp = 0000H, TCRmp outputs INTTMmp and
stops counting until the next start trigger (INTTMmn of the master channel) has been input. The output level of TOmp
becomes active one count clock after generation of INTTMmn from the master channel, and inactive when TCRmp =
0000H.
one-count mode, counts the duty factor, and outputs a PWM waveform from the TOmq pin. The TCRmq register loads the
value of the TDRmq register, using INTTMmn of the master channel as a start trigger, and starts counting down. When
TCRmq = 0000H, the TCRmq register outputs INTTMmq and stops counting until the next start trigger (INTTMmn of the
master channel) has been input. The output level of TOmq becomes active one count clock after generation of INTTMmn
from the master channel, and inactive when TCRmq = 0000H.
time.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values
For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the
Timer/counter register mn (TCRmn) of the master channel operates in the interval timer mode and counts the periods.
The TCRmp register of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM
In the same way as the TCRmp register of the slave channel 1, the TCRmq register of the slave channel 2 operates in
When channel 0 is used as the master channel as above, up to seven types of PWM signals can be output at the same
Caution To rewrite both timer data register mn (TDRmn) of the master channel and the TDRmp register of the
Remark
Remark
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period
Duty factor 1 [%] = {Set value of TDRmp (slave 1)}/{Set value of TDRmn (master) + 1} × 100
Duty factor 2 [%] = {Set value of TDRmq (slave 2)}/{Set value of TDRmn (master) + 1} × 100
Note
slave channel 1, write access is necessary at least twice. Since the values of the TDRmn and TDRmp
registers are loaded to the TCRmn and TCRmp registers after INTTMmn is generated from the master
channel, if rewriting is performed separately before and after generation of INTTMmn from the master
channel, the TOmp pin cannot output the expected waveform. To rewrite both the TDRmn register of
the master and the TDRmp register of the slave, be sure to rewrite both the registers immediately
after INTTMmn is generated from the master channel (This applies also to the TDRmq register of the
slave channel 2).
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04
78K0R/KF3-L, 78K0R/KG3-L:
p: Slave channel number 1, q: Slave channel number 2
When m = 0: n < p < q ≤ 7
When m = 1: n < p < q ≤ 3
(Where p and q are consecutive integers greater than n)
Although the duty factor exceeds 100% if the set value of TDRmp (slave 1) > {set value of TDRmn
(master) + 1} or if the {set value of TDRmq (slave 2)} > {set value of TDRmn (master) + 1}, it is
summarized into 100% output.
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as
the slave channel.
mn = 00, 02, 04, 10
Note
CHAPTER 8 TIMER ARRAY UNIT
482