UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 701

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(1) Register setting
SMRmn
SCRmn
SDRmn
Operation clock (f
channel n
0: Prescaler output clock CKm0
1: Prescaler output clock CKm1
SMRmr
Caution For the UART reception, be sure to set SMRmr of channel r that is to be paired with channel n.
(Remarks are listed on the next page.)
set by the SPSm register
set by the SPSm register
(a) Serial mode register mn (SMRmn)
(b) Serial mode register mr (SMRmr)
(c) Serial communication operation setting register mn (SCRmn)
(d) Serial data register mn (SDRmn) (lower 8 bits: RXDq)
Same setting value as CKSmn
bit
CKSmn
CKSmr
TXEmn
0/1
0/1
15
15
15
15
0
Figure 14-83. Example of Contents of Registers for UART Reception of UART
CCSmn
Setting of parity bit
00B: No parity
01B: No parity judgment
10B: Appending Even parity
11B: Appending Odd parity
RXEmn
CCSmr
MCK
14
14
14
14
0
0
1
) of
DAPmn
13
13
13
13
0
0
0
Baud rate setting
CKPmn
12
12
12
12
0
0
0
0: Forward (normal) reception
1: Reverse reception
11
11
11
11
0
0
0
EOCmn
10
10
10
10
0
0
1
(UART0 to UART4) (1/2)
PTCmn1
0/1
0
9
9
0
9
9
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
PTCmn0
STSmn
STSmr
0/1
1
8
8
0
8
8
0
DIRmn
0/1
0
0
7
7
7
7
SISmn0
SISmr0
0/1
0
0
6
6
6
6
SLCmn1
5
1
5
1
5
0
5
CHAPTER 14 SERIAL ARRAY UNIT
Receive data register
SLCmn0
4
0
4
0
4
1
4
RXDq
Operation mode of channel n
Operation mode of channel r
0
0
3
0
3
3
3
1: Buffer empty interrupt
0: Transfer end interrupt
0: Transfer end interrupt
Setting of data length
MDmn2
DLSmn2
MDmr2
1
2
0
2
0
2
2
DLSmn1
MDmn1
MDmr1
0/1
1
1
1
1
1
1
MDmn0
DLSmn0
MDmr0
0/1
0/1
0
0
0
0
0
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