UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 926

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
Notes 1. This is not mounted onto 40-pin product of the 78K0R/KC3-L.
Remark f
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
System clock
CPU
Flash memory
RAM
Port (latch)
Timer array unit
Real-time counter (RTC)
Watchdog timer
Clock output/buzzer output
A/D converter
Programmable gain amplifier
Comparator
Serial array unit (SAU)
Serial interface (IICA)
Multiplier/divider
DMA controller
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt function
Main system clock
Subsystem clock
Note 1
f
IL
2. Read P140 as P130 if using the 78K0R/KF3-L or 78K0R/KG3-L.
3. This is not mounted onto 40-pin and 44-pin products of the 78K0R/KC3-L.
4. 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L only.
f
f
f
f
IH
X
EX
XT
IL
Note 4
:
:
:
Item
: External main system clock
: XT1 oscillation clock
Internal high-speed oscillation clock
X1 oscillation clock
Internal low-speed oscillation clock
Note 3
Note 1
f
f
f
f
IH
X
EX
XT
Note 3
Note 4
Clock supply to the CPU is stopped.
Operation stopped
Operation stopped (the X1 and X2 pins are input port mode)
Clock input invalid (the pin is input port mode)
Operation stopped (the XT1 and XT2 pins are input port mode)
Operation stopped
Operation stopped (The value, however, is retained when the voltage is at least the power-on-
clear detection voltage.)
Set P140 to low-level output. The port pins except for P140 become high impedance.
Operation stopped
Detection operation possible
Operation stopped (however, operation continues at LVI reset)
Operation stopped
Table 21-1. Operation Statuses During Reset Period
During Reset Period
CHAPTER 21 RESET FUNCTION
Note 2
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