UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 1159

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Previous
version
(U19291E)
3rd edition
Edition
Change of Figure 5-13. Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte:
LVIOFF = 1))
Change of Figure 5-14. Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Enabled Is Set (Option Byte:
LVIOFF = 0))
Change of 5.6 Controlling Clock
Addition of Notes 3 and 4 to 5.6.6 CPU clock status transition diagram
Change of 6.1.1 Independent channel operation function
Change of 6.1.2 Simultaneous channel operation function
Change of Figure 6-1. Entire Configuration of Timer Array Unit TAUS
Addition of Figure 6-2. Internal Block Diagram of Channel of Timer Array Unit
TAUS
Change of Figure 6-21. Format of Timer Output Mode Register 0 (TOM0)
Change of Figure 6-22. Format of Input Switch Control Register (ISC)
Change of description of operation start in Figure 6-39. Operation Procedure of
Interval Timer/Square Wave Output Function
Change of description in 6.7.2 Operation as external event counter
Addition of Caution to 6.7.5 Operation as input signal high-/low-level width
measurement
Change of description in 6.8.2 Operation as PWM function
Change of Note in Figure 7-2. Format of Peripheral Enable Register 0 (PER0)
Addition of Note to Figure 7-18. Procedure for Starting Operation of Real-Time
Counter
Change of 10.4.3 Setting window open period of watchdog timer (deletion of
window open period 25% setting)
Change of Figure 11-5. A/D Converter Sampling and A/D Conversion Timing
Change of description in 11.6 (9) Conversion results just after A/D conversion
start
Change of Table 11-4. Resistance and Capacitance Values of Equivalent Circuit
(Reference Values)
Change of Note 2 in Figure 12-4. Format of Serial Clock Select Register 0 (SPS0)
Change of description of the MD0n0 bit in Figure 12-5. Format of Serial Mode
Register 0n (SMR0n) (2/2)
Addition of Note to Figure 12-6. Format of Serial Communication Operation
Setting Register 0n (SCR0n) (2/3)
Change of description in 12.3 (5) Higher 7 bits of the serial data register 0n
(SDR0n)
Change of Figure 12-8. Format of Serial Flag Clear Trigger Register 0n (SIR0n)
Change of Figure 12-9. Format of Serial Status Register 0n (SSR0n)
Change of Figure 12-25. Procedure for Stopping Master Transmission
Change of Figure 12-27. Timing Chart of Master Transmission (in Single-
Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of Figure 12-29. Timing Chart of Master Transmission (in Continuous
Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Description
APPENDIX B REVISION HISTORY
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 6 TIMER
ARRAY UNIT
CHAPTER 7 REAL-TIME
COUNTER
CHAPTER 10
WATCHDOG TIMER
CHAPTER 11 A/D
CONVERTER
CHAPTER 12 SERIAL
ARRAY UNIT
Chapter
(4/7)
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