UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 371

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
7.6 Controlling Clock
7.6.1 Example of setting 8 MHz internal high-speed oscillator
option byte to FBH. Use the system clock control register (CKC) to specify the division ratio for the clock to be supplied to
the CPU/peripheral hardware clock after releasing reset. When using the default division setting (f
register is not required to be set.
7.6.2 Example of setting 1 MHz internal high-speed oscillator
option byte to FDH. Use the system clock control register (CKC) to specify the division ratio for the clock to be supplied to
the CPU/peripheral hardware clock after releasing reset. When using the default division setting (f
CKC register is not required to be set.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
To use the 8 MHz internal high-speed oscillation clock as the CPU/peripheral hardware clock (f
[Option byte setting]
Set address 000C1H to FBH.
[Register settings]
<1> Use the MDIV2 to MDIV0 bits of the CKC register to specify the division ratio for the CPU/peripheral hardware
To use the 1 MHz internal high-speed oscillation clock as the CPU/peripheral hardware clock (f
[Option byte setting]
Set address 000C1H to FDH.
[Register settings]
<1> Use the MDIV2 to MDIV0 bits of the CKC register to specify the division ratio for the CPU/peripheral hardware
Note
Note
clock.
clock.
(000C1H)
(000C1H)
Option
Option
CKC
CKC
byte
byte
CLS bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), be sure to clear CLS bit
to 0.
CLS bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), be sure to clear CLS bit
to 0.
LVIOFF bit: Set this bit to 0 to turn on the LVI by default when releasing the power-on-reset.
LVIOFF bit: Set this bit to 0 to turn on the LVI by default when releasing the power-on-reset.
CLS
CLS
7
1
7
0
7
1
7
0
Note
Note
CSS
CSS
6
1
6
0
6
1
6
0
MCS
MCS
1
0
1
0
5
5
5
5
MCM0
MCM0
4
1
4
4
1
4
0
0
3
3
1
3
1
1
3
1
CHAPTER 7 CLOCK GENERATOR
FRQSEL2
FRQSEL2
MDIV2
MDIV2
0/1
0/1
2
2
0
2
1
2
FRQSEL1
FRQSEL1
MDIV1
MDIV1
0/1
0/1
1
1
1
1
0
1
CLK
CLK
IH
/2 = 4 MHz), the CKC
IH
), set 000C1H of the
), set 000C1H of the
/2 = 0.5 MHz), the
LVIOFF
LVIOFF
MDIV0
MDIV0
0/1
0/1
0
1
0
0
1
0
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