UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 616

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F0060H
(15) Noise filter enable register 0 (NFEN0)
Symbol
NFEN0
Notes 1. 78K0R/KF3-L, 78K0R/KG3-L only.
Caution Be sure to clear bits 7 to 3, and 1 to “0” in the 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L. Be
The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data
input pin to each channel.
Disable the noise filter of the pin used for CSI or simplified I
this register to 0.
Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to
1.
When the noise filter is enabled, CPU/ peripheral hardware clock (f
detection.
The NFEN0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the NFEN0 register to 00H.
SNFEN30
SNFEN20
Set SNFEN40 to 1 to use the R
Clear SNFEN40 to 0 to use the other than RxD4 pin.
Set SNFEN30 to 1 to use the R
Clear SNFEN30 to 0 to use the other than RxD3 pin.
Set SNFEN20 to 1 to use the R
Clear SNFEN20 to 0 to use the other than RxD2 pin.
Set the SNFEN10 bit to 1 to use the R
Clear the SNFEN10 bit to 0 to use the other than RxD1 pin.
2. 78K0R/KF3-L (
SNFEN40
SNFEN10
sure to clear bits 7, 5, 3, and 1 to “0” in the 78K0R/KF3-L (
78K0R/KG3-L (
(
μ
0
1
0
1
0
1
0
1
7
0
After reset: 00H
PD78F1027, 78F1028) and 78K0R/KG3-L (
Note 1
Note 1
Figure 14-19. Format of Noise Filter Enable Register 0 (NFEN0) (1/2)
SNFEN30
Noise filter OFF
Noise filter ON
Noise filter OFF
Noise filter ON
Noise filter OFF
Noise filter ON
Noise filter OFF
Noise filter ON
6
μ
μ
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: RxD1/SDA10/SI10/INTP1/P31 pin
78K0R/KF3-L, 78K0R/KG3-L:
PD78F1027, 78F1028), 78K0R/KG3-L (
Note 1
PD78F1013, 78F1014). Be sure to clear bits 7, 5, and 3 to “0” in the 78K0R/KF3-L
R/W
X
X
X
D4 pin.
D3 pin.
D2 pin.
5
0
Use of noise filter of R
Use of noise filter of R
X
D1 pin.
SNFEN20
Use of noise filter of R
4
Use of noise filter of R
Note 1
μ
X
PD78F1029, 78F1030).
X
D4 pin (R
2
D2 pin (R
C communication, by clearing the corresponding bit of
3
0
X
D3 pin (R
μ
X
RxD1/SDA10/SI10/P03 pin
X
D4/SI40/INTP2/P51
PD78F1029, 78F1030) only.
D2/SDA20/SI20/P143)
X
CHAPTER 14 SERIAL ARRAY UNIT
D1 pin
CLK
SNFEN10
μ
X
D3/P14)
) is synchronized with 2-clock match
PD78F1010, 78F1011, 78F1012) and
2
SNFEN40
Note 2
)
1
Note 2
SNFEN00
0
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