UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 356

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F00F0H
Address: F00F1H
Address: F00F2H
Symbol
Symbol
Symbol
(PER0)
(PER1)
(PER2)
PER0
PER1
PER2
Bit 2
Bit 3
Bit 0
Notes 1. This is not mounted onto 40-pin product of the 78K0R/KC3-L.
Caution Be sure to clear bits 0, 1, 3, and 6 (40-pin product of the 78K0R/KC3-L: bits 0, 1, 3, 4, 6,
Figure 7-10. Format of Peripheral Enable Registers 0, 1, 2 (PER0, PER1, PER2)
RTCEN
OACMPEN
SAU0EN
TAU0EN
<7>
2. This is not mounted onto 40-pin and 44-pin products of the 78K0R/KC3-L.
7
0
7
0
0
1
0
1
0
1
Note 1
After reset: 00H
After reset: 00H
After reset: 00H
and 7, 44-pin product of the 78K0R/KC3-L: bits 0, 1, 3, 4, and 6) of the PER0 register, bits
0 to 2 and 4 to 7 of the PER1 register, and bits 1 to 7 of the PER2 register to 0.
Stops input clock supply.
• SFR used by the serial array unit 0 cannot be written.
• The serial array unit 0 is in the reset status.
Enables input clock supply.
• SFR used by the serial array unit 0 can be read and written.
Stops input clock supply.
• SFR used by the comparator and programmable gain amplifier cannot be written.
• The comparator and programmable gain amplifier is in the reset status.
Enables input clock supply.
• SFR used by the comparator and programmable gain amplifier can be read and written.
Stops input clock supply.
• SFR used by timer array unit 0 cannot be written.
• Timer array unit 0 is in the reset status.
Enables input clock supply.
• SFR used by timer array unit 0 can be read and written.
(78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L) (2/2)
6
0
6
0
6
0
Control of comparator and programmable gain amplifier input clock supply
R/W
R/W
R/W
ADCEN
<5>
5
0
5
0
Control of serial array unit 0 input clock supply
Control of timer array unit 0 input clock supply
IICAEN
<4>
4
0
4
0
Note 2
OACMPEN
<3>
3
0
3
0
CHAPTER 7 CLOCK GENERATOR
SAU0EN
<2>
2
0
2
0
1
0
1
0
1
0
TAU0EN
<0>
0
0
0
0
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