UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 954

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(b) When LVI default start function enabled is set (LVIOFF = 0)
• When starting operation
• When stopping operation
Figure 23-9 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this
timing chart correspond to <1> to <3> above.
Cautions 1. Even when the LVI default start function is used, if it is set to LVI operation prohibition by the
Be sure to clear (0) the LVION bit by using a 1-bit memory manipulation instruction.
<1>
<2>
<3>
<4>
Start in the following initial setting state.
Release the interrupt mask flag of LVI (LVIMK).
Execute the EI instruction (when vector interrupts are used).
Clear bit 1 (LVIMD) of the LVIM register to 0 (generates interrupt signal when the level is detected)
(default value).
2. When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the LVIRF flag may
•
•
•
•
•
Set bit 7 (LVION) of the low-voltage detection register (LVIM) to 1 (enables LVI operation)
Set bit 1 (LVIMD) of the LVIM register to 1 (generates reset when the level is detected)
Set bit 0 (LVIF) of the LVIM register to 0 (Detects falling edge “Supply voltage (V
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
(V
Set the low-voltage detection level selection register (LVIS) to 0EH (default value: V
V ).
(V
software, it operates as follows:
For details of the RESF register, see CHAPTER 21 RESET FUNCTION.
become 1 from the beginning due to the power-on waveform.
DD
LVI
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts after
))
)”)
reset release. There is a period when low-voltage detection cannot be performed normally,
however, when a reset occurs due to WDT and illegal instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
LVION = 1 is set upon reset occurrence, and the CPU starts operating without waiting for
the LVI stabilization time.
CHAPTER 23 LOW-VOLTAGE DETECTOR
DD
) ≥ detection voltage
LVI
= 2.07 V ±0.1
μ
s max.,
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