UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 596

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03),
SMRmn
(3) Serial mode register mn (SMRmn)
Symbol
The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation
clock (f
UART, or I
UART mode.
Rewriting the SMRmn register is prohibited when the register is in operation (when SEmn = 1). However, the
MDmn0 bit can be rewritten during operation.
The SMRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SMRmn register to 0020H.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
(Remark is listed on the next page.)
F0150H, F0151H (SMR10) to F0156H, F0157H (SMR13),
F0208H, F0209H (SMR20) , F020AH, F020BH (SMR21)
Operation clock (f
higher 7 bits of the SDRmn register, a transfer clock (f
Transfer clock f
error controller. When CCSmn = 0, the division ratio of operation clock (f
SDRmn register.
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
CKS
CCS
CKS
STS
MCK
mn
mn
mn
mn
15
0
1
0
1
0
1
), specify whether the serial clock (f
2
C), and an interrupt source. This register is also used to invert the level of the receive data only in the
Operation clock CKm0 set by the SPSm register
Operation clock CKm1 set by the SPSm register
Divided operation clock f
Clock input f
Only software trigger is valid (selected for CSI, UART transmission, and simplified I
Valid edge of the R
CCS
mn
14
Figure 14-7. Format of Serial Mode Register mn (SMRmn) (1/3)
TCLK
13
0
MCK
is used for the shift register, communication controller, output controller, interrupt controller, and
SCK
) is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the
from the SCKp pin (slave transfer in CSI mode)
12
0
X
Dq pin (selected for UART reception)
11
0
MCK
specified by the CKSmn bit
10
Selection of operation clock (f
0
Selection of transfer clock (f
SCK
Selection of start trigger source
9
0
) may be input or not, set a start trigger, an operation mode (CSI,
STS
mn
8
TCLK
After reset: 0020H
) is generated.
7
0
mn0
TCLK
SIS
MCK
6
) of channel n
) of channel n
CHAPTER 14 SERIAL ARRAY UNIT
MCK
5
1
) is set by the higher 7 bits of the
R/W
4
0
2
3
0
C).
mn2
MD
2
mn1
MD
1
mn0
MD
0
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