UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 913

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
Notes 1. That os not mounted onto 40-pin product of the 78K0R/KC3-L.
Remark f
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Item
System clock
CPU
Flash memory
RAM
Port (latch)
Timer array unit
Real-time counter (RTC)
Watchdog timer
Clock output/buzzer output
A/D converter
Programmable gain amplifier
Comparator
Serial array unit (SAU)
Serial interface (IICA)
Multiplier/divider
DMA controller
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt function
Main system clock
Subsystem
clock
f
IL
2. Those are not mounted onto 40-pin and 44-pin products of the 78K0R/KC3-L.
3. 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L only.
Note 1
f
f
f
f
f
IH
IH20
X
EX
XT
IL
HALT Mode Setting
Note 3
:
:
:
:
:
: 20 MHz internal high-speed oscillation clock
Internal high-speed oscillation clock
X1 clock
External main system clock
XT1 clock
Internal low-speed oscillation clock
Note 2
f
f
f
f
Note 1
IH
X
EX
XT
, f
Note 2
Note 3
IH20
Internal High-Speed Oscillation
Clock supply to the CPU is stopped
Operation continues (cannot
be stopped)
Status before HALT mode
was set is retained
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Oscillates
• WTON = 1 and WDSTBYON = 0: Stops
Operation stopped
Operation stopped
The value is retained
Status before HALT mode was set is retained
Operable
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Operates
• WTON = 1 and WDSTBYON = 0: Stops
Operable
High-Speed Oscillation Clock
Clock (f
When CPU Is Operating on
Table 20-1. Operating Statuses in HALT Mode (1/2)
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
IH
) or 20 MHz Internal
(f
IH20
)
Status before HALT mode was set is retained
Operation continues (cannot
be stopped)
Cannot operate
Status before HALT mode was set is retained
When CPU Is Operating on
X1 Clock (f
X
CHAPTER 20 STANDBY FUNCTION
)
Cannot operate
Operation continues (cannot
be stopped)
External Main System Clock
When CPU Is Operating on
(f
EX
)
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