UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 112

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
3.2.14 P140 to P145 (port 14)
clock/buzzer output, serial interface data I/O, and clock I/O.
port input mode register 14 (PIM14).
in 1-bit units using port output mode register 14 (POM14).
Notes 1. PCLBUZ/INTP7 is shared with P55, in the 78K0R/KF3-L.
(1) Port mode
(2) Control mode
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
P140/PCLBUZ0/INTP6
P141/PCLBUZ1/INTP7
P142/SCK20/SCL20
P143/SI20/RxD2/SDA20
P144/SO20/TxD2
P145/TI07/TO07
P140 to P145 function as an I/O port.
Input to the P142 and P143 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
Output from the P142 to P144 pins can be specified as normal CMOS output or N-ch open-drain output (V
The following operation modes can be specified in 1-bit units.
P140 to P145 function as an I/O port. P140 to P145 can be set to input or output port in 1-bit units using port mode
register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14).
P140 to P145 function as timer I/O, external interrupt request input, clock/buzzer output, serial interface data I/O, and
clock I/O.
(a) INTP6, INTP7
(b) PCLBUZ0, PCLBUZ1
(c) TI07
(d) TO07
(e) SI20
(f) SO20
2. TI07/TO07 is shared with P54, in the 78K0R/KF3-L.
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
These are the clock/buzzer output pins.
This is a pin for inputting an external count clock/capture trigger to 16-bit timer 07.
This is a timer output pin of 16-bit timer 07.
This is a serial data input pin of serial interface CSI20.
This is a serial data output pin of serial interface CSI20.
(
μ
PD78F10xx: xx = 10, 11, 12,
78K0R/KF3-L
27, 28)
−
−
Note 2
Note 1
√
√
√
√
These pins also function as timer I/O, external interrupt request input,
CHAPTER 3 PIN FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
(
μ
PD78F10xx: xx = 13, 14,
78K0R/KG3-L
29, 30)
√
√
√
√
√
√
DD
tolerance)
112