UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 890

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Note
Cautions 1. Be sure to clear bits 6 and 7 of the IF2H register to 0 (except for
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
The MK0L, MK0H, MK1L, MK1H, MK2L, and MK2H registers can be set by a 1-bit or 8-bit memory manipulation
instruction. When the MK0L and MK0H registers, the MK1L and MK1H registers, and the MK2L and MK2H registers
are combined to form 16-bit registers MK0, MK1, and MK2, they can be set by a 16-bit memory manipulation
instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
Address: FFFD1H
Symbol
Figure 18-7. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (2/2)
IF2H
Those are only mounted in the
increases by 2 clocks.
2. When operating a timer, serial interface, or A/D converter after standby release, operate it once
3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation
78F1030).
after clearing the interrupt request flag. An interrupt request flag may be set by noise.
instruction (CLR1). When describing in C language, use a bit manipulation instruction such as
“IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler must be a 1-bit memory
manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction such as
“IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.
In this case, even if the request flag of the another bit of the same interrupt request flag register
(IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is cleared to 0
at “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit memory manipulation
instruction in C language.
CSIIF41
mov a, IF0L
and a, #0FEH
mov IF0L, a
XXIFX
SRIF4
7
0
1
After reset: 00H
Note
No interrupt request signal is generated
Interrupt request is generated, interrupt request status
CSIIF40
STIF4
6
Note
μ
R/W
PD78F1027, 78F1028, 78F1029, and 78F1030.
MDIF
<5>
SREIF2
<4>
Interrupt request flag
TMIF12
<3>
CHAPTER 18 INTERRUPT FUNCTIONS
TMIF11
<2>
μ
PD78F1027, 78F1028, 78F1029,
TMIF10
<1>
SREIF4
PIF11
<0>
Note
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