UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 936

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(2) When LVI is ON upon power application (option byte: LVIOFF = 0)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(when X1 oscillation
oscillation clock (f
V
V
Internal high-speed
Internal reset signal
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 23 LOW-
Remark V
V
POR
PDR
system clock (f
LVI
CPU
= 1.61 V (TYP.)
= 1.59 V (TYP.)
= 2.07 V (TYP.)
Supply voltage
High-speed
is selected)
1.8 V
5.
2.
3.
4.
Operation
(V
MX
VOLTAGE DETECTOR).
V
V
V
Note 1
IH
stops
DD
0 V
LVI
)
)
The operation guaranteed range is 1.8 V ≤ V
when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the
RESET pin.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register
(OSTC) to confirm the lapse of the oscillation stabilization time. To use the XT1 clock
function for confirmation of the lapse of the stabilization time.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal high-
speed oscillation clock.
The following times are required between reaching the POC detection voltage (1.61 V (TYP.)) and starting
normal operation.
• When the time to reach 2.07 V (TYP.) from 1.61 V (TYP.) is less than 5.8 ms:
• When the time to reach 2.07 V (TYP.) from 1.61 V (TYP.) is greater than 5.8 ms:
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
LVI
POR
PDR
Figure 22-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
)
A POC processing time of 2.12 to 5.84 ms is required between reaching 1.61 V (TYP.) and starting
normal operation.
A reset processing time of 195 to 341
operation.
:
: POC power supply fall detection voltage
: POC power supply rise detection voltage
LVI detection voltage
Wait for oscillation
accuracy stabilization
Note 4
POC processing time
Reset processing time
oscillation clock)
(internal high-speed
(V
reset (default)
Normal operation
to be used for
LVI
Set LVI
specified by software
Starting oscillation is
= 2.07 V)
Note 3
Note 2
and Low-Voltage Detector (2/2)
(oscillation
Reset
period
stop)
μ
Wait for oscillation
accuracy stabilization
s is required between reaching 2.07 V (TYP.) and starting normal
Reset processing time
(about 195 to 341 s)
used for interrupt
Set LVI to be
DD
oscillation clock)
(internal high-speed
Normal operation
≤ 5.5 V. To make the state at lower than 1.8 V reset state
specified by software
Starting oscillation is
CHAPTER 22 POWER-ON-CLEAR CIRCUIT
μ
Note 3
Note 2
(oscillation
Reset
period
stop)
(V
to be used for
reset (default)
Note 4
Wait for oscillation
accuracy stabilization
LVI
Set LVI
= 2.07 V)
oscillation clock)
(internal high-speed
POC processing time
Reset processing time
Normal operation
specified by software
Starting oscillation is
voltage (V
Change LVI
detection
Note 3
Note 2
LVI
Note 5
)
, use the timer
Operation stops
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