UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 607

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03),
SSRmn
Symbol
Remark m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
F0140H, F0141H (SSR10) to F0146H, F0147H (SSR13),
F0200H, F0201H (SSR20), F0202H, F0203H (SSR21)
<Clear condition>
<Set condition>
<Clear condition>
<Set condition>
OVF
FEF
PEF
mn
mn
mn
0
1
0
1
0
1
• 1 is written to the FECTmn bit of the SIRmn register.
• A stop bit is not detected when UART reception ends.
• 1 is written to the PECTmn bit of the SIRmn register.
• The parity of the transmit data and the parity bit do not match when UART reception ends (parity error).
• No ACK signal is returned from the slave channel at the ACK reception timing during I
<Clear condition>
• 1 is written to the OVCTmn bit of the SIRmn register.
<Set condition>
• Even though receive data is stored in the SDRmn register, that data is not read and transmit data or the next
• Transmit data is not ready for slave transmission or transmission and reception in CSI mode.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L
78K0R/KF3-L
78K0R/KG3-L
78K0R/KG3-L
not detected).
receive data is written while the RXEmn bit of the SCRmn register is set to 1 (reception or transmission and
reception mode in each communication mode).
15
0
No error occurs.
An error occurs (during UART reception).
No error occurs.
An error occurs (during UART reception) or ACK is not detected (during I
No error occurs.
An error occurs
14
Figure 14-11. Format of Serial Status Register mn (SSRmn) (2/2)
0
13
0
μ
μ
μ
μ
PD78F1010, 78F1011, 78F1012 :
PD78F1027, 78F1028 :
PD78F1013, 78F1014 :
PD78F1029, 78F1030 :
12
0
11
0
Framing error detection flag of channel n
Overrun error detection flag of channel n
Parity error detection flag of channel n
10
0
9
0
8
0
After reset: 0000H
7
0
mn = 00 to 03
mn = 00 to 03, 10 to 13
mn = 00 to 03, 10 to 13, 20, 21
mn = 00 to 03, 10 to 13
mn = 00 to 03, 10 to 13, 20, 21
TSF
mn
CHAPTER 14 SERIAL ARRAY UNIT
6
BFF
mn
2
5
C transmission).
R
4
0
2
C transmission (ACK is
3
0
FEF
mn
2
PEF
mn
1
OVF
mn
0
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