UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 844

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(3) Multiplication/division data register C (MDCL, MDCH)
The MDCH and MDCL registers store remainder value of the operation result in the division mode. They are not
used in the multiplication mode.
The MDCH and MDCL registers can be read by a 16-bit manipulation instruction.
Reset signal generation clears these registers to 0000H.
Caution The MDCH and MDCL registers values read during division operation processing (while the
Remark
The register configuration differs between when multiplication is executed and when division is executed, as follows.
• Register configuration during multiplication
• Register configuration during division
Address: F00E0H, F00E1H, F00E2H, F00E3H
Symbol
MDCH
Symbol
MDCL
MDAL (bits 15 to 0) × MDAH (bits 15 to 0) = [MDBH (bits 15 to 0), MDBL (bits 15 to 0)]
[MDAH (bits 15 to 0), MDAL (bits 15 to 0)] ÷ [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] =
[MDAH (bits 15 to 0), MDAL (bits 15 to 0)] ⋅⋅⋅ [MDCH (bits 15 to 0), MDCL (bits 15 to 0)]
DIVMODE
<Multiplier A>
0
1
MDCH
MDCL
Table 16-4. Functions of MDCH and MDCL Registers During Operation Execution
multiplication/division control register (MDUC) is 81H) will not be guaranteed.
DIVMODE: Bit 7 of the multiplication/division control register (MDUC)
15
15
Figure 16-4. Format of Multiplication/Division Data Register C (MDCH, MDCL)
MDCH
MDCL
14
14
<Dividend>
<Quotient>
Multiplication mode
Division mode
MDCH
MDCL
13
13
<Multiplier B>
Operation Mode
MDCH
MDCL
12
12
F00E3H
F00E1H
MDCH
MDCL
11
11
MDCH
MDCL
10
10
After reset: 0000H, 0000H R
MDCH
MDCL
9
9
MDCH
MDCL
8
8
Setting
<Remainder>
<Divisor>
−
−
MDCH
MDCL
<Product>
7
7
MDCH
MDCL
6
6
CHAPTER 16 MULTIPLIER/DIVIDER
MDCH
MDCL
5
5
MDCH: Remainder (higher 16 bits)
MDCL: Remainder (lower 16 bits)
MDCH
MDCL
4
4
F00E2H
F00E0H
MDCH
MDCL
Operation Result
3
3
MDCH
MDCL
2
2
−
MDCH
MDCL
1
1
MDCH
MDCL
0
0
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