UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 1160

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Previous
version
(U19291E)
3rd edition
Edition
Change of Figure 12-31. Example of Contents of Registers for Master Reception
of 3-Wire Serial I/O (CSI00, CSI01, CSI10) (2/2)
Change of Figure 12-34. Procedure for Resuming Master Reception
Change of Figure 12-35. Timing Chart of Master Reception (in Single-Reception
Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of Figure 12-36. Flowchart of Master Reception (in Single-Reception
Mode)
Change of Figure 12-39. Procedure for Stopping Master
Transmission/Reception
Change of Figure 12-41. Timing Chart of Master Transmission/Reception (in
Single-Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of Figure 12-43. Timing Chart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of transfer rate in 12.5.4 Slave transmission
Change of Figure 12-47. Procedure for Stopping Slave Transmission
Change of Figure 12-49. Timing Chart of Slave Transmission (in Single-
Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of Figure 12-51. Timing Chart of Slave Transmission (in Continuous
Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of transfer rate in 12.5.5 Slave reception
Change of Figure 12-53. Example of Contents of Registers for Slave Reception
of 3-Wire Serial I/O (CSI00, CSI01, CSI10) (2/2)
Change of Figure 12-56. Procedure for Resuming Slave Reception
Change of Figure 12-57. Timing Chart of Slave Reception (in Single-Reception
Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of Figure 12-58. Flowchart of Slave Reception (in Single-Reception
Mode)
Change of transfer rate in 12.5.6 Slave transmission/reception
Change of Figure 12-61. Procedure for Stopping Slave Transmission/Reception
Change of Figure 12-63. Timing Chart of Slave Transmission/Reception (in
Single-Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of Figure 12-65. Timing Chart of Slave Transmission/Reception (in
Continuous Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of Note in 12.5.7 Calculating transfer clock frequency
Change of Note 2 in Table 12-2. Selection of Operation Clock
Addition of Caution to 12.6 Operation of UART (UART0, UART1) Communication
Change of Figure 12-70. Procedure for Stopping UART Transmission
Change of Figure 12-72. Timing Chart of UART Transmission (in Single-
Transmission Mode)
Change of Figure 12-74. Timing Chart of UART Transmission (in Continuous
Transmission Mode)
Change of description in 12.6.2 UART reception
Change of Figure 12-76. Example of Contents of Registers for UART Reception
of UART (UART0, UART1) (2/2)
Change of Figure 12-79. Procedure for Resuming UART Reception
Change of Figure 12-80. Timing Chart of UART Reception
Description
APPENDIX B REVISION HISTORY
CHAPTER 12 SERIAL
ARRAY UNIT
Chapter
(5/7)
1160