UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 742

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
14.8.6 Procedure for processing errors that occurred during simplified I
Figure 14-110 and 14-111.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remark
Reads serial data register mn
(SDRmn).
Reads serial status register mn
(SSRmn).
Writes 1 to serial flag clear trigger
register mn (SIRmn).
Reads serial data register mn
(SDRmn).
Reads serial status register mn (SSRmn).
Writes serial flag clear trigger register mn
(SIRmn).
Sets the STmn bit of serial channel stop
register m (STm) to 1.
Creates stop condition.
Creates start condition.
Sets the SSmn bit of serial channel start
register m (SSm) to 1.
The procedure for processing errors that occurred during simplified I
Software Manipulation
Figure 14-111. Processing Procedure in Case of Parity Error (ACK error) in Simplified I
Software Manipulation
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
Figure 14-110. Processing Procedure in Case of Overrun Error
The BFFmn bit of the SSRmn register
is set to 0 and channel n is enabled to
receive data.
Error flag is cleared.
The BFFmn bit of the SSRmn register is
set to 0 and channel n is enabled to
receive data.
Error flag is cleared.
The SEmn bit of serial channel enable
status register m (SEm) is set to 0 and
channel n stops operation.
The SEmn bit of serial channel enable
status register m (SEm) is set to 1 and
channel n is enabled to operate.
Hardware Status
Hardware Status
mn = 02, r = 10
mn = 02, 10, r = 10, 20
2
C (IIC10, IIC20) communication is described in
2
C (IIC10, IIC20) communication
CHAPTER 14 SERIAL ARRAY UNIT
Error can be cleared only during
This is to prevent an overrun error if the
next reception is completed during error
processing.
Error type is identified and the read
value is used to clear error flag.
reading, by writing the value read from
the SSRmn register to the SIRmn
register without modification.
This is to prevent an overrun error if the
next reception is completed during
error processing.
Error type is identified and the read
value is used to clear error flag.
Error can be cleared only during
reading, by writing the value read from
the SSRmn register to the SIRmn
register without modification.
Slave is not ready for reception
because ACK is not returned.
Therefore, a stop condition is created,
the bus is released, and
communication is started again from
the start condition. Or, a restart
condition is generated and
transmission can be redone from
address transmission.
Remark
Remark
2
C Mode
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