UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 774

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(6) IICA low-level width setting register (IICWL)
(7) IICA high-level width setting register (IICWH)
This register is used to set the low-level width of the SCL0 pin signal that is output by serial interface IICA.
The IICWL register can be set by an 8-bit memory manipulation instruction.
Set the IICWL register while operation of I
Reset signal generation sets this register to FFH.
This register is used to set the high-level width of the SCL0 pin signal that is output by serial interface IICA.
The IICWH register can be set by an 8-bit memory manipulation instruction.
Set the IICWL register while operation of I
Reset signal generation sets this register to FFH.
Remark
Figure 15-11. Format of IICA High-Level Width Setting Register (IICWH)
Figure 15-10. Format of IICA Low-Level Width Setting Register (IICWL)
Address: F0232H
Address: F0233H
For how to set the transfer clock by using the IICWL and IICWH registers, see 15.4.2 Setting
transfer clock by using IICWL and IICWH registers.
Symbol
Symbol
IICWH
IICWL
7
7
After reset: FFH R/W
After reset: FFH R/W
6
6
2
2
C is disabled (bit 7 (IICE) of IICA control register 0 (IICCTL0) is 0).
C is disabled (bit 7 (IICE) of IICA control register 0 (IICCTL0) is 0).
5
5
4
4
3
3
CHAPTER 15 SERIAL INTERFACE IICA
2
2
1
1
0
0
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