UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 563

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UPD78F1000GB-GAF-AX

Manufacturer Part Number
UPD78F1000GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet

Specifications of UPD78F1000GB-GAF-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1000GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Note 2
Note 3
Notes 1.
Cautions 1. Be sure to clear the following bits to 0.
Remarks 1.
Symbol
Address: FFF31H
ADS
Note 2
2.
3.
Note 2
2.
2 Set a channel to be used for A/D conversion in the input mode by using port mode registers 2, 15,
3. Do not set the pin that is set by the A/D port configuration register (ADPC) as digital I/O by the
4. Select the output signal (PGAO) of the programmable gain amplifier from the PGAI pin as the
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L only.
Setting permitted
Setting prohibited
Note 2
Note 2
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: bits 4, 5, 7
78K0R/KF3-L, 78K0R/KG3-L:
and 8 (PM2, PM15, PM8).
ADS register.
analog input after setting the operation of the programmable gain amplifier (refer to 13.4.1 Basic
operations of A/D converter).
×: don’t care
Note 3
P20/ANI0 to P27/ANI7, P150/ANI8 to P152/ANI10: 78K0R/KC3-L (48-pin) and 78K0R/KD3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P153/ANI11: 78K0R/KE3-L, 78K0R/KF3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P157/ANI15: 78K0R/KG3-L
P20/ANI0 to P27/ANI7, P150/ANI8, P151/ANI9:
7
0
Figure 13-8. Format of Analog Input Channel Specification Register (ADS) (2/2)
After reset: 00H
ADOAS
Scan mode (ADMD = 1)
ADOAS
Note 1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
6
Note 1
ADS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
Other than the above
5
0
ADS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
4
0
ADS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
bits 4 to 7
78K0R/KC3-L (40-pin, 44-pin)
ADS3
ADS0
3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Scan 0
PGAO
PGAO
PGAO
PGAO
PGAO
PGAO
PGAO
PGAO
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
CHAPTER 13 A/D CONVERTER
ADS2
2
Analog input channel
Scan 1
Setting prohibited
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ADS1
1
Scan 2
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ADS0
Scan 3
ANI10
0
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
563

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