UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 592

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F00F0H
Address: F00F1H
PER1
(1) Peripheral enable registers 0, 1 (PER0, PER1)
Symbol
Symbol
PER0
PER0 and PER1 register are used to enable or disable supplying the clock to the peripheral hardware. Clock
supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of PER0 register to 1.
In the 78K0R/KF3-L and 78K0R/KG3-L, be sure to set bit 3 (SAU1EN) of PER0 register to 1 when using serial
array unit 1, in the 78K0R/KF3-L (
to set bit 0 (SAU2EN) of PER1 register to 1 when using serial array unit 2.
The PER0 and PER1 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the PER0 and PER1 register to 00H.
Cautions 1. When setting serial array unit m, be sure to set the SAUmEN bit to 1 first. If SAUmEN = 0,
Notes 1.
Note
RTCEN
2.
3.
4.
SAUmEN
2. After setting the SAUmEN bit to 1, be sure to set serial clock select register m (SPSm) after 4
(Caution 3 and Remark are listed on the next page.)
<7>
0
1
7
0
After reset: 00H
After reset: 00H
That is not provided in 40-pin product of the 78K0R/KC3-L.
That is not provided in 40-pin and 44-pin products of the 78K0R/KC3-L.
78K0R/KF3-L and 78K0R/KG3-L only.
78K0R/KF3-L (
Note 1
writing to a control register of serial array unit m is ignored, and, even if the register is read,
only the default value is read.
Note that this does not apply to the following registers.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L (
78K0R/KF3-L (
or more f
ISC, NFEN0, PIM3, PIM7, POM3, POM7, PM3, PM7, P3, and P7 registers.
ISC, NFEN0, PIM0, PIM1, PIM14, POM0, POM1, POM14, PM0, PM1, PM4, PM14, P0, P1, P4,
and P14 registers.
ISC, NFEN0, PIM0, PIM1, PIM14, POM0, POM1, POM14, PM0, PM1, PM4, PM5, PM14, P0, P1,
P4, P5, and P14 registers.
Figure 14-5. Format of Peripheral Enable Register 0, 1 (PER0, PER1)
Stops supply of input clock.
• SFR used by serial array unit m cannot be written.
• Serial array unit m is in the reset status.
Enables input clock supply.
• SFR used by serial array unit m can be read/written.
CLK
6
0
6
0
μ
clocks have elapsed.
R/W
R/W
PD78F1027, 78F1028) and 78K0R/KG3-L (
μ
μ
PD78F1010, 78F1011, 78F1012), 78K0R/KG3-L (
PD78F1027, 78F1028), 78K0R/KG3-L (
μ
ADCEN
PD78F1027, 78F1028) and 78K0R/KG3-L (
<5>
5
0
Control of serial array unit m input clock supply
IICAEN
<4>
4
0
Note 2
SAU1EN
<3>
3
0
Note 3
CHAPTER 14 SERIAL ARRAY UNIT
μ
μ
PD78F1029, 78F1030):
SAU0EN
PD78F1029, 78F1030) only.
<2>
2
0
μ
μ
PD78F1029, 78F1030), be sure
PD78F1013, 78F1014):
TAU1EN
<1>
1
0
Note 3
TAU0EN
SAU2EN
<0>
<0>
Note 3
Note 4
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