UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 423

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F01BCH, F01BDH
Address: F01E4H, F01E5H
(11) Timer output level register m (TOLm)
Symbol
Symbol
TOL0
TOL1
The TOLm register is a register that controls the timer output level of each channel.
The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer
output signal while the timer output is enabled (TOEmn = 1) in the slave channel output mode (TOMmn = 1). In
the master channel output mode (TOMmn = 0), this register setting is invalid.
The TOLm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOLm register can be set with an 8-bit memory manipulation instruction with TOLmL.
Reset signal generation clears this register to 0000H.
Caution Be sure to clear bits 15 to 8 of the TOL0 register and bits 15 to 4 of the TOL1 register to “0”.
Remarks 1.
TOL
mn
15
15
0
1
0
0
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Positive logic output (active-high)
Inverted output (active-low)
14
14
0
0
If the value of this register is rewritten during timer operation, the timer output is inverted when the
timer output signal changes next, instead of immediately after the register value is rewritten.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
After reset: 0000H
13
13
Figure 8-24. Format of Timer Output Level register m (TOLm)
After reset: 0000H
0
0
12
12
0
0
11
11
0
0
R/W
R/W
10
10
0
0
Control of timer output level of channel n
9
0
9
0
8
0
8
0
TOL
07
7
7
0
mn = 00 to 07, 10 to 13
TOL
06
6
6
0
TOL
05
CHAPTER 8 TIMER ARRAY UNIT
5
5
0
TOL
04
4
4
0
TOL
TOL
03
13
3
3
TOL
TOL
02
12
2
2
TOL
TOL
01
11
1
1
TOL
TOL
00
10
0
0
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