UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 353
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UPD78F1000GB-GAF-AX
Manufacturer Part Number
UPD78F1000GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1000GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1000GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
(6) 20 MHz internal high-speed oscillation control register (DSCCTL)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Note Bit 3 is read-only.
Cautions 1. 20 MHz internal oscillation can only be used if V
This register controls the 20 MHz internal high-speed oscillation clock (DSC) function.
This register can be used to control oscillation of the 20 MHz internal high-speed oscillation clock (f
20 MHz internal high-speed oscillation clock (f
The DSCCTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: F00F6H
DSCCTL
Symbol
Figure 7-9. Format of 20 MHz Internal High-Speed Oscillation Control Register (DSCCTL)
2. Set the SELDSC bit when 100
3. The internal high-speed oscillator must be operated (HIOSTOP = 0) when DSCON = 1.
4. If 1 MHz internal oscillation is selected by using the option byte, 20 MHz internal high-speed
oscillation cannot be used. Do not set (1) the DSCON bit.
SELDSC
DSCON
DSCS
7
0
0
1
0
1
0
1
After reset: 00H
Not supplied
Supplied (The CPU/peripheral hardware clock (f
speed oscillation clock.)
Does not select 20 MHz internal high-speed oscillation (clock selected by the system clock
control register (CKC) is supplied to f
Selects 20 MHz internal high-speed oscillation (20 MHz internal high-speed oscillation is
supplied to f
Stopped
Operated
Selection of 20 MHz internal high-speed oscillation for CPU/peripheral hardware clock (f
6
0
Operating or stopping 20 MHz internal high-speed oscillation clock (f
CLK
R/W
)
Note
20 MHz internal high-speed oscillation supply status flag
5
0
μ
IH20
s have elapsed after the DSCON bit has been set with V
) as the CPU/peripheral hardware clock.
4
0
CLK
)
DD
DSCS
<3>
≥ 2.7 V.
CLK
) operates on the 20 MHz internal high-
CHAPTER 7 CLOCK GENERATOR
SELDSC
<2>
1
0
IH20
IH20
)
DSCON
) and select the
<0>
CLK
)
DD
≥ 2.7 V.
353
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