UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 919

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware
(2) STOP mode release
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The STOP mode can be released by the following two sources.
(a) Release by unmasked interrupt request
Standby release signal
When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization
time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt
acknowledgment is disabled, the next address instruction is executed.
Remark The broken lines indicate the case when the interrupt request that has released the standby mode is
2. To stop the internal low-speed oscillation clock in the STOP mode, use an option byte to stop the
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
4. The STOP instruction cannot be executed when the CPU operates on the 20 MHz internal high-speed
for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart
the peripheral hardware.
watchdog timer operation in the HALT/STOP mode (bit 0 (WDSTBYON) of 000C0H = 0), and then
execute the STOP instruction.
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the internal
high-speed oscillation clock before the execution of the STOP instruction. Before changing the CPU
clock from the internal high-speed oscillation clock to the high-speed system clock (X1 oscillation)
after the STOP mode is released, check the oscillation stabilization time with the oscillation
stabilization time counter status register (OSTC).
oscillation clock. Be sure to execute the STOP instruction after shifting to internal high-speed
oscillation clock operation.
(X1 oscillation)
Status of CPU
system clock
High-speed
acknowledged.
(1) When high-speed system clock (X1 oscillation) is used as CPU clock
Figure 20-5. STOP Mode Release by Interrupt Request Generation (1/2)
Normal operation
system clock)
(high-speed
Oscillates
instruction
STOP
Oscillation stopped
STOP mode
Interrupt
request
stabilization time
(set by OSTS)
Oscillation
Oscillates
CHAPTER 20 STANDBY FUNCTION
(2 clocks)
Wait
Normal operation
system clock)
(high-speed
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