UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 794

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Notes 1. The wait time is calculated as follows.
Remark STT:
(Communication reservation)
2. The communication reservation operation executes a write to the IICA shift register (IICA) when a stop
MSTS: Bit 7 of IICA status register (IICS)
IICA:
IICWL: IICA low-level width setting register
IICWH: IICA high-level width setting register
t
f
(IICWL setting value + IICWH setting value + 4) + t
condition interrupt request occurs.
F
CLK
:
:
Bit 1 of IICA control register 0 (IICCTL0)
IICA shift register
SDA0 and SCL0 signal falling times
CPU/peripheral hardware clock frequency
Figure 15-27. Communication Reservation Protocol
Note 2
Yes
Cancel communication
reservation
Define communication
reservation
MOV IICA, #××H
MSTS = 0?
SET1 STT
Wait
DI
EI
(Generate start condition)
No
F
× 2 × f
Sets STT flag (communication reservation)
Defines that communication reservation is in effect
(defines and sets user flag to any part of RAM)
Secures wait time
Confirmation of communication reservation
Clear user flag
IICA write operation
CHAPTER 15 SERIAL INTERFACE IICA
CLK
[clocks]
Note 1
by software.
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