UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 463

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Note 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
TAU
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
TAU
stop
78K0R/KF3-L, 78K0R/KG3-L:
78K0R/KC3-L (40-pin):
78K0R/KC3-L (44-pin, 48-pin):
78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
Sets the TAU0EN and TAU1EN bits of peripheral enable
registers 0, 2 (PER0, PER2) to 1.
Sets timer clock select register m (TPSm).
Sets timer mode register mn (TMRmn) (determines
operation mode of channel).
Sets TSmn bit to 1.
Set values of only the CISmn1 and CISmn0 bits of the
TMRmn register can be changed.
The TDRmn register can always be read.
The TCRmn register can always be read.
The TSRmn register can always be read.
Set values of the TOMmn, TOLmn, TOmn, and TOEmn
bits cannot be changed.
The TTmn bit is set to 1.
The TAU0EN and TAU1EN bits of the PER0 and PER2
registers are cleared to 0.
Figure 8-56. Operation Procedure When Input Pulse Interval Measurement Function Is Used
Determines clock frequencies of CKm0 and CKm1.
The TSmn bit automatically returns to 0 because it is a
trigger bit.
The TTmn bit automatically returns to 0 because it is a
trigger bit.
Software Operation
Note
Note
mn = 02 to 07
mn = 00 to 07
mn = 00 to 07
mn = 00 to 07, 10 to 13
TAU0EN bit of the PER2 register
TAU0EN or TAU1EN bit of the PER0 register
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
TEmn = 1, and count operation starts.
Counter (TCRmn) counts up from 0000H. When the TImn
pin input valid edge is detected, the count value is
transferred (captured) to timer data register mn (TDRmn).
At the same time, the TCRmn register is cleared to
0000H, and the INTTMmn signal is generated.
If an overflow occurs at this time, the OVF bit of timer
status register mn (TSRmn) is set; if an overflow does not
occur, the OVF bit is cleared.
After that, the above operation is repeated.
TEmn = 0, and count operation stops.
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
Timer/counter register mn (TCRmn) is cleared to 0000H
at the count clock input.
When the MDmn0 bit of the TMRmn register is 1,
INTTMmn is generated.
The TCRmn register holds count value and stops.
The OVF bit of the TSRmn register is also held.
All circuits are initialized and SFR of each channel is
also initialized.
CHAPTER 8 TIMER ARRAY UNIT
Hardware Status
463