UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 857

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
17.4 Operation of DMA Controller
17.4.1 Operation procedure
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
<1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set the
<2> Set an SFR address, a RAM address, the number of times of transfer, and a transfer mode of DMA transfer to
<3> The DMA controller waits for a DMA trigger when DSTn = 1. Use 81H to write with an 8-bit manipulation
<4> When a software trigger (STGn) or a start source trigger specified by the IFCn3 to IFCn0 bits is input, a DMA
<5> Transfer is completed when the number of times of transfer set by the DBCn register reaches 0, and transfer is
<6> Stop the operation of the DMA controller by clearing the DENn bit to 0 when the DMA controller is not used.
Remark
DENn bit to 1. Use 80H to write with an 8-bit manipulation instruction.
DMA SFR address register n (DSAn), DMA RAM address register n (DRAn), DMA byte count register n (DBCn),
and DMA mode control register n (DMCn).
instruction.
transfer is started.
automatically terminated by occurrence of an interrupt (INTDMAn).
n: DMA channel number (n = 0, 1)
Setting DSAn, DRAn, DBCn, and DMCn
Receiving DMA acknowledge
Transmitting DMA request
DRAn = DRAn + 1 (or + 2)
Figure 17-6. Operation Procedure
DBCn = DBCn − 1
DMA trigger = 1?
DBCn = 0000H ?
INTDMAn = 1
DMA transfer
DENn = 1
DSTn = 1
DSTn = 0
DENn = 0
Yes
Yes
No
No
CHAPTER 17 DMA CONTROLLER
Set by software program
Operation by DMA
controller (hardware)
Set by software program
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