UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 845

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
16.3 Register Controlling Multiplier/Divider
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The multiplier/divider is controlled by using the multiplication/division control register (MDUC).
(1) Multiplication/division control register (MDUC)
The MDUC register is an 8-bit register that controls the operation of the multiplier/divider.
The MDUC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: F00E8H
Note The DIVST bit can only be set (1) in the division mode. In the division mode, division operation is started by
Cautions 1. Do not rewrite the DIVMODE bit during operation processing (while the DIVST bit is 1). If it is
Symbol
MDUC
setting (1) the DIVST bit. The DIVST bit is automatically cleared (0) when the operation ends. In the
multiplication mode, operation is automatically started by setting the multiplier and multiplicand to
multiplication/division data register A (MDAH, MDAL), respectively.
2. The DIVST bit cannot be cleared (0) by using software during division operation processing
DIVMODE
DIVMODE
DIVST
rewritten, the operation result will be an undefined value.
(while the DIVST bit is 1).
<7>
Figure 16-5. Format of Multiplication/Division Control Register (MDUC)
0
1
0
1
Note
After reset: 00H
Multiplication mode
Division mode
Division operation processing complete
Starts division operation/division operation processing in progress
6
0
R/W
5
0
Operation mode (multiplication/division) selection
4
0
Division operation start/stop
3
0
CHAPTER 16 MULTIPLIER/DIVIDER
2
0
1
0
DIVST
<0>
845