UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 206

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
5.2.6 Port 5
Note TI06/TO06 and TI07/TO07 are shared only in the 78K0R/KC3-L and 78K0R/KD3-L. The 78K0R/KE3-L does not
Remark √: Mounted
mode register 5 (PM5). When the P50 to P53 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 5 (PU5).
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
P50/TI06/TO06
P51/TI07/TO07
P52/RTC1HZ/
SLTI/SLTO
P53
Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port
This port can also be used for real-time counter correction clock output and timer I/O.
Reset signal generation sets port 5 to input mode.
Figures 5-11 to 5-13 show block diagrams of port 5.
Caution 1. To use P50/TI06/TO06 and P51/TI07/TO07 as a general-purpose port, set bits 6 and 7 (TO06 and
Remark n = 0, 1
have a sharing function.
2. To use P52/RTC1HZ/SLTI/SLTO as a general-purpose port, check which timer I/O pin of which
3. In the case of the 78K0R/KC3-L (40-pin), be sure to clear bit2 of the PM5 register to “0” after the
TO07) of timer output register 0 (TO0) and bits 6 and 7 (TOE06 and TOE07) of timer output enable
register 0 (TOE0) to “0”, which is the same as their default status setting.
channel n is selected in the input switching control register (ISC) setting. Also, set bit n (TO0n) of
timer output register 0 (TO0) and bit n (TOE0n) of timer output enable register 0 (TOE0) to “0”,
which is the same setting as in the initial state of each.
reset release.
(
μ PD78F100y: y = 0 to 3)
40-pin
−
78K0R/KC3-L
CHAPTER 5 PORT FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
√
√
−
44-pin
√
(
μ PD78F100y: y = 1 to 3)
78K0R/KC3-L (48-pin)
√
√
√
−
(
μ PD78F100y: y = 4 to 6)
78K0R/KD3-L
√
√
√
−
(
μ PD78F100y: y = 7 to 9)
78K0R/KE3-L
P51
P50
√
√
Note
Note
206