UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 242

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(6) A/D port configuration register (ADPC)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Symbol
Address: F0017H
ADPC
This register switches the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI11/P153 pins to digital I/O of port or analog
input of A/D converter.
The ADPC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 10H.
Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode register 2
ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
Remark P20/ANI0 to P27/ANI7, P150/ANI8, and P151/ANI9: 78K0R/KC3-L (40-pin, 44-pin)
0
0
0
0
0
0
0
0
0
0
0
0
1
7
0
Other than the above
P20/ANI0 to P27/ANI7, P150/ANI8 to P152/ANI10: 78K0R/KC3-L (48-pin), 78K0R/KD3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P153/ANI11: 78K0R/KE3-L
0
0
0
0
0
0
0
0
1
1
1
1
0
After reset: 10H
2. Do not set the pin that is set by the ADPC register as digital I/O by the analog input channel
3. Be sure to first set the ADCEN bit of peripheral enable register 0 (PER0) to 1 when setting up
and 15 (PM2, PM15).
specification register (ADS).
the ADPC register. If ADCEN = 0, writing to the ADPC register is ignored and specified
values are returned to the initial values.
0
0
0
0
1
1
1
1
0
0
0
0
0
Figure 5-41. Format of A/D Port Configuration Register (ADPC)
6
0
CHAPTER 5 PORT FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
0
0
1
1
0
0
1
1
0
0
1
1
0
R/W
5
0
0
1
0
1
0
1
0
1
0
1
0
1
0
ANI11
/P153
Setting prohibited
A
A
A
A
A
A
A
A
A
D
A
A
A
ADPC4
ANI10
/P152
A
A
A
A
A
A
A
A
A
A
A
D
D
Port 15
4
/P151
ANI9
D
D
D
A
A
A
A
A
A
A
A
A
A
Analog input (A)/digital I/O (D) switching
/P150
ANI8
ADPC3
A
A
A
A
A
A
A
A
A
D
D
D
D
3
ANI7
/P27
A
A
D
D
D
D
D
A
A
A
A
A
A
ANI6
/P26
A
A
A
A
A
A
A
D
D
D
D
D
D
ADPC2
2
ANI5
/P25
D
D
D
D
D
D
D
A
A
A
A
A
A
ANI4
/P24
A
A
A
A
A
D
D
D
D
D
D
D
D
Port 2
ADPC1
ANI3
/P23
A
A
D
D
D
D
D
D
D
D
D
A
A
1
ANI2
/P22
A
A
A
D
D
D
D
D
D
D
D
D
D
ANI1
/P21
ADPC0
D
D
D
D
D
D
D
D
D
D
D
A
A
0
ANI0
/P20
A
D
D
D
D
D
D
D
D
D
D
D
D
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