UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 829

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The meanings of <3> to <10> in (2) Address ~ data ~ data in Figure 15-32 are explained below.
Note If the transmitted address does not match the address of the slave device, the slave device does not return
Remark <1> to <15> in Figure 15-32 represent the entire procedure for communicating data using the I
<3> If the address received matches the address of a slave device
<4> The master device issues an interrupt (INTIICA: end of address transmission) at the falling edge of the 9th
<5> The master device writes the data to transmit to the IICA shift register (IICA) and releases the wait status
<6> If the slave device releases the wait status (WREL = 1), the master device starts transferring data to the
<7> When data transfer is complete, the slave device sends an ACK by hardware to the master device. The
<8> The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
<9> The master device writes the data to transmit to the IICA register and releases the wait status that it set by
<10> The slave device reads the received data and releases the wait status (WREL = 1). The master device then
an ACK to the master device (NACK: SDA0 = 1). The slave device also does not issue the INTIICA interrupt
(address match) and does not set a wait status. The master device, however, issues the INTIICA interrupt
(end of address transmission) regardless of whether it receives an ACK or NACK.
hardware to the master device. The ACK is detected by the master device (ACKD = 1) at the rising edge of
the 9th clock.
clock, and the slave device whose address matched the transmitted slave address also issues an interrupt
(INTIICA: address match). The master device and slave device also set a wait status (SCL0 = 0)
the addresses match.
that it set by the master device.
slave device.
ACK is detected by the master device (ACKD = 1) at the rising edge of the 9th clock.
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
the master device.
starts transferring data to the slave device.
Figure 15-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 15-32
(2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 15-32 (3) Data ~ data ~
stop condition shows the processing from <7> to <15>.
CHAPTER 15 SERIAL INTERFACE IICA
Note
, that slave device sends an ACK by
2
C bus.
Note
when
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