UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 716

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Reception interrupt
Here is the flow of signal processing.
<1> The wakeup signal is detected by detecting an interrupt edge (INTP0) on a pin. When the wakeup signal is
<2> When the start bit of SBF is detected, reception is started and serial data is sequentially stored in the RXDk
<3> When SBF reception has been correctly completed, start channel 7 of the timer array unit 0 and measure the bit
<4> Calculate a baud rate error from the bit interval of sync field (SF). Stop UARTk once and adjust (re-set) the baud
<5> The checksum field should be distinguished by software. In addition, processing to initialize UARTk after the
Edge detection
Remark
R
detected, enable reception of UARTk (RXEmn = 1) and wait for SBF reception.
register (= bits 7 to 0 of serial data register mn (SDRmn)) at the set baud rate. When the stop bit is detected, the
reception end interrupt request (INTSRk) is generated. When data of low levels of 11 bits or more is detected as
SBF, it is judged that SBF reception has been correctly completed. If data of low levels of less than 11 bits is
detected as SBF, it is judged that an SBF reception error has occurred, and the system returns to the SBF
reception wait status.
interval (pulse width) of the sync field (see 8.7.5
measurement).
rate.
checksum field is received and to wait for reception of SBF should also be performed by software.
X
Dk (input)
(INTSRk)
LIN Bus
Capture
(INTP0)
timer
m: Unit number (m = 0, 1), n: Channel number (n = 1, 3),
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 01, k = 0
78K0R/KF3-L, 78K0R/KG3-L:
k: Number of UART used for LIN communication (k = 0, 3)
Disable
Wakeup signal
<1>
frame
Enable
Figure 14-94. Reception Operation of LIN
Disable
Sync break
13-bit SBF
reception
field
<2>
<3>
Sync field
reception
mn = 13, k = 3
SF
Enable
Operation as input signal high-/low-level width
<4>
Identification
reception
field
CHAPTER 14 SERIAL ARRAY UNIT
ID
Data filed Data filed Checksum
reception
Data
reception
Data
reception
Data
field
<5>
716