UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 711

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
14.6.4 Procedure for processing errors that occurred during UART (UART0 to UART4) communication
Figures 14-90 and 14-91.
Remark m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Reads serial data register mn
(SDRmn).
Reads serial status register mn
(SSRmn).
Writes 1 to serial flag clear trigger
register mn (SIRmn).
Reads serial data register mn
(SDRmn).
Reads serial status register mn
(SSRmn).
Writes serial flag clear trigger register mn
(SIRmn).
Sets the STmn bit of serial channel stop
register m (STm) to 1.
Synchronization with other party of
communication
Sets the SSmn bit of serial channel start
register m (SSm) to 1.
The procedure for processing errors that occurred during UART (UART0 to UART4) communication is described in
Software Manipulation
Software Manipulation
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L (
78K0R/KF3-L (
78K0R/KG3-L (
78K0R/KG3-L (
Figure 14-90. Processing Procedure in Case of Parity Error or Overrun Error
μ
μ
μ
μ
PD78F1010, 78F1011, 78F1012):
PD78F1027, 78F1028):
PD78F1013, 78F1014):
PD78F1029, 78F1030):
Figure 14-91. Processing Procedure in Case of Framing Error
The BFFmn bit of the SSRmn register
is set to 0 and channel n is enabled to
receive data.
Error flag is cleared.
The BFFmn bit of the SSRmn register
is set to 0 and channel n is enabled to
receive data.
Error flag is cleared.
The SEmn bit of serial channel enable
status register m (SEm) is set to 0 and
channel n stops operating.
The SEmn bit of serial channel enable
status register m (SEm) is set to 1 and
channel n is enabled to operate.
Hardware Status
Hardware Status
mn = 00 to 03
mn = 00 to 03, 10 to 13
mn = 00 to 03, 10 to 13, 20, 21
mn = 00 to 03, 10 to 13
mn = 00 to 03, 10 to 13, 20, 21
CHAPTER 14 SERIAL ARRAY UNIT
Error can be cleared only during
This is to prevent an overrun error if the
next reception is completed during error
processing.
Error type is identified and the read
value is used to clear error flag.
reading, by writing the value read from
the SSRmn register to the SIRmn
register without modification.
This is to prevent an overrun error if the
next reception is completed during error
processing.
Error type is identified and the read
value is used to clear error flag.
Error can be cleared only during
reading, by writing the value read from
the SSRmn register to the SIRmn
register without modification.
Synchronization with the other party of
communication is re-established and
communication is resumed because it is
considered that a framing error has
occurred because the start bit has been
shifted.
Remark
Remark
711