UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 764
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UPD78F1000GB-GAF-AX
Manufacturer Part Number
UPD78F1000GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1000GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1000GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F0230H
IICCTL0
Symbol
Notes 1. The IICA status register (IICS), the STCF and IICBSY bits of the IICA flag register (IICF), and the
Caution If the operation of I
WREL
Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level.
Condition for clearing (IICE = 0)
• Cleared by instruction
• Reset
LREL
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL = 0)
• Automatically cleared after execution
• Reset
When the WREL bit is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status
(TRC = 1), the SDA0 line goes into the high impedance state (TRC = 0).
Condition for clearing (WREL = 0)
• Automatically cleared after execution
• Reset
IICE
IICE
<7>
0
1
0
1
0
1
Notes 2, 3
Notes 2, 3
2. The signal of this bit is invalid while IICE0 is 0.
3. When the LREL and WREL bits are read, 0 is always read.
After reset: 00H
CLD and DAD bits of IICA control register 1 (IICCTL1) are reset.
low level, and the digital filter is turned on (DFC bit of IICCTL1 register = 1), a start condition
will be inadvertently detected immediately. In this case, set (1) the LREL bit by using a 1-bit
memory manipulation instruction immediately after enabling operation of I
Stop operation. Reset the IICA status register (IICS)
Enable operation.
Normal operation
This exits from the current communications and sets standby mode. This setting is automatically cleared
to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCL0 and SDA0 lines are set to high impedance.
The following flags of IICA control register 0 (IICCTL0) and the IICA status register (IICS) are cleared to
0.
• STT • SPT • MSTS • EXC • COI • TRC • ACKD • STD
Do not cancel wait
Cancel wait. This setting is automatically cleared after wait is canceled.
LREL
<6>
Figure 15-6. Format of IICA Control Register 0 (IICCTL0) (1/4)
WREL
<5>
R/W
2
C is enabled (IICE = 1) when the SCL0 line is high level, the SDA0 line is
SPIE
<4>
Exit from communications
WTIM
<3>
I
2
C operation enable
Wait cancellation
Condition for setting (IICE = 1)
• Set by instruction
Condition for setting (LREL = 1)
• Set by instruction
Condition for setting (WREL = 1)
• Set by instruction
ACKE
Note 1
<2>
. Stop internal operation.
CHAPTER 15 SERIAL INTERFACE IICA
STT
<1>
SPT
<0>
2
C (IICE = 1).
764
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