UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 873

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Maskable
Software
Reset
Interrupt
Notes 1.
Type
2.
3.
4.
5.
Default
Priority
Note 1
41
42
43
44
45
46
47
−
−
The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 47 indicate the lowest priority.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 18-1.
INTST4, INTCSI40, INTSR4, INTCSI41 are only mounted in the 78K0R/KF3-L (
78F1028) and the 78K0R/KG3-L (
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1.
When the instruction code in FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
INTTM10
INTTM11
INTTM12
INTSRE2
INTMD
INTST4
/INTCSI40
INTSR4
/INTCSI41
BRK
RESET
POC
LVI
WDT
TRAP
Name
UART4 transmission transfer end
or buffer empty interrupt/CSI40
transfer end or buffer empty
interrupt
empty interrupt
Execution of BRK instruction
Low-voltage detection
Overflow of watchdog timer
End of timer channel 10 count
or capture
End of timer channel 11 count
or capture
End of timer channel 12 count
or capture
UART2 reception
communication error occurrence
End of A/D conversion
UART4 reception transfer
end/CSI41 transfer end or buffer
RESET pin input
Power-on-clear
Execution of illegal
instruction
Interrupt Source
Table 18-1. Interrupt Source List (3/3)
Note 5
Trigger
μ
PD78F1029 and 78F1030).
Note 4
Internal
External
Internal/
−
−
Address
CHAPTER 18 INTERRUPT FUNCTIONS
005AH
005CH
005EH
007EH
Vector
0056H
0058H
0060H
0062H
0000H
Table
Configuration
Type
Basic
(D)
(A)
−
Note 2
−
−
−
−
−
−
−
√
√
√
√
√
√
−
−
−
−
−
−
−
√
√
√
√
√
√
μ
−
−
−
−
−
−
−
√
√
√
√
√
√
PD78F1027 and
−
−
−
−
−
−
−
√
√
√
√
√
√
−
−
−
−
−
−
−
√
√
√
√
√
√
Note
Note
√
√
√
√
√
√
√
√
√
√
√
3
3
Note
Note
873
√
√
√
√
√
√
√
√
√
√
√
3
3