UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 441

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(b) Set/reset timing
Master channel
Remarks 1. Internal reset signal: TOmn pin reset/toggle signal
Slave channel
To realize 0%/100% output at PWM output, the TOmn pin/TOmn bit set timing at master channel timer interrupt
(INTTMmn) generation is delayed by 1 count clock by the slave channel.
If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Figure 8-35 shows the set/reset operating statuses where the master/slave channels are set as follows.
Master channel:
Slave channel:
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Note
Internal set signal:
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
78K0R/KC3-L (44-pin, 48-pin): mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
p: Slave channel number
When m = 0: Master channel n = 0, 2, 4, 6, n < p ≤ 7
When m = 1: Master channel n = 0, 2, n < p ≤ 3
(Where p is a consecutive integer greater than n)
(Internal signal)
Internal reset
Count clock
Internal set
TOmn pin/
TOmp pin/
INTTMmn
INTTMmp
to_reset
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be
used as the slave channel.
TOmn
TOmp
signal
signal
f
CLK
Figure 8-35. Set/Reset Timing Operating Statuses
TOEmn = 1, TOMmn = 0, TOLmn = 0
TOEmp = 1, TOMmp = 1, TOLmp = 0
TOmn pin set signal
Delays to_reset by 1 count
clock with slave channel
Toggle
Note
mn = 02 to 07
mn = 00 to 07
mn = 00 to 07, 10 to 13
Set
CHAPTER 8 TIMER ARRAY UNIT
Reset
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