UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 372

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
7.6.3 Example of setting 20 MHz internal high-speed oscillator
option byte to FBH. After releasing reset, set the operation speed mode control register (OSMC) and then the 20 MHz
internal high-speed oscillation control register (DSCCTL).
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
To use the 20 MHz internal high-speed oscillation clock as the CPU/peripheral hardware clock (f
[Option byte setting]
Set address 000C1H to FBH.
[Register settings] Set the register in the order of <1> to <5> below.
<1> Set the OSMC register so that the microcontroller operates at a frequency exceeding 10 MHz.
<2> Set (1) the DSCON bit of the DSCCTL register to operate the 20 MHz internal high-speed oscillator.
<3> Set (1) the DSCON bit and then wait for 100
<4> Set (1) the SELDSC bit of the DSCCTL register to switch the internal high-speed oscillation clock from 8 MHz to 20
<5> Use the MDIV2 to MDIV0 bits of the CKC register to specify the division ratio for the CPU/peripheral hardware
Note
Note
MHz.
clock.
(000C1H)
DSCCTL
DSCCTL
OSMC
Option
CKC
byte
RTCLPC bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), be sure to clear
RTCLPC bit to 0.
CLS bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), be sure to clear CLS bit
to 0.
LVIOFF bit: Set this bit to 0 to turn on the LVI by default when releasing the power-on-reset.
RTCLPC bit
RTCLPC
CLS
7
1
7
0
7
0
7
0
7
0
Note
Note
Note
: Set this bit to 1 to operate only the watch in sub-HALT mode (ultra-low current
consumption).
CSS
6
1
6
0
6
0
6
0
6
0
MCS
1
0
0
0
0
5
5
5
5
5
μ
s.
MCM0
4
1
4
4
4
4
0
0
0
0
DSCS
DSCS
3
1
3
0
3
0
3
0
3
1
CHAPTER 7 CLOCK GENERATOR
FRQSEL2
SELDSC
SELDSC
MDIV2
0/1
2
0
2
0
2
0
2
1
2
FRQSEL1
MDIV1
FLPC
0/1
1
1
1
0
1
0
1
0
1
CLK
), set 000C1H of the
DSCON
DSCON
LVIOFF
MDIV0
FSEL
0/1
0
1
0
1
0
1
0
1
0
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