UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 884

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(4) External interrupt rising edge enable register 0 (EGP0), external interrupt falling edge enable register 0
Address: FFF38H
Symbol
EGP0
Address: FFF39H
Symbol
EGN0
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(EGN0)
These registers specify the valid edge for INTP0 to INTP7
The EGP0 and EGN0 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Table 18-3 shows the ports corresponding to the EGPn and EGNn bits.
Note
Caution Select the port mode by clearing the EGPn and EGNn bits to 0 because an edge may be
Remark 78K0R/KC3-L (40-pin):
EGP7
EGN7
EGPn
7
7
0
0
1
1
Figure 18-5. Format of External Interrupt Rising Edge Enable Register 0 (EGP0)
After reset: 00H
After reset: 00H
Note
Note
EGP7
EGP0
EGP1
EGP2
EGP3
EGP4
EGP5
EGP6
Detection Enable Bit
Those are not provided in the 40-pin product of the 78K0R/KC3-L.
detected when the external interrupt function is switched to the port function.
78K0R/KC3-L (44-pin, 48-pin), 78K0R/KD3-L, 78K0R/KE3-L: n = 0 to 7
78K0R/KF3-L, 78K0R/KG3-L:
Note
EGNn
EGP6
EGN6
6
6
0
1
0
1
Table 18-3. Ports Corresponding to EGPn and EGNn Bits
and External Interrupt Falling Edge Enable Register 0 (EGN0)
EGN7
EGN1
EGN2
EGN3
EGN4
EGN5
EGN6
EGN0
R/W
R/W
Edge detection disabled
Falling edge
Rising edge
Both rising and falling edges
EGP5
EGN5
Note
5
5
P120
P31
P32
P80
P70
P71
P72
P82
Note
EGP4
EGN4
Edge Detection Port
INTPn pin valid edge selection (n = 0 to 7
4
4
Note
EGP3
EGN3
.
3
3
CHAPTER 18 INTERRUPT FUNCTIONS
EGP2
EGN2
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTP7
2
2
Interrupt Request Signal
Note
n = 0 to 6
n = 0 to 7
EGN1
EGP1
Note
1
1
)
EGN0
EGP0
0
0
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