UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 828

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(2) Address ~ data ~ data
Notes 1. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during master transmission.
(communication status)
(communication status)
(8 or 9 clock wait)
(wait cancellation)
(wait cancellation)
(8 or 9 clock wait)
(transmit/receive)
(transmit/receive)
(ACK detection)
(ACK detection)
(SP detection)
Master side
(ST detection)
(ACK control)
(ACK control)
Slave side
(SP trigger)
SDA0 (bus)
(ST trigger)
SCL0 (bus)
Bus line
(clock line)
(data line)
(interrupt)
(interrupt)
2. To cancel slave wait, write “FFH” to IICA or set the WREL bit.
INTIICA
MSTS
INTIICA
MSTS
WTIM
WREL
WREL
ACKD
ACKE
ACKD
WTIM
ACKE
IICA
SPT
TRC
IICA
STD
SPD
TRC
STT
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/4)
: Wait state by slave device
: Wait state by master and slave devices
H
H
H
L
L
L
H
<3>
L
H
H
L
L
W ACK
Figure 15-32. Example of Master to Slave Communication
Note 1
<5>
<4>
<6>
D
1
7
Note 2
D
1
6
D
1
5
D
1
4
D
1
3
CHAPTER 15 SERIAL INTERFACE IICA
D
1
2
D
1
1
D
1
0
<7>
ACK
<9>
Note 1
<8>
<10>
D
2
7
Note 2
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