UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 691

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(1) Register setting
Note
Remarks 1. m: Unit number (m = 0 to 2), n: Channel number (n = 0, 2), q: UART number (p = 0 to 4)
SMRmn
SCRmn
SDRmn
SOLm
(a) Serial mode register mn (SMRmn)
(b) Serial communication operation setting register mn (SCRmn)
(d) Serial output level register m (SOLm) … Sets only the bits of the target channel.
(c) Serial data register mn (SDRmn) (lower 8 bits: TXDq)
This bit is invalid while operating serial allay unit 2.
2.
CKSmn
TXEmn
0/1
Operation clock (f
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
15
15
15
15
1
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L (
78K0R/KF3-L (
78K0R/KG3-L (
78K0R/KG3-L (
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
0
Figure 14-75. Example of Contents of Registers for UART Transmission of UART
Setting of parity bit
00B: No parity
01B: Appending 0 parity
10B: Appending Even parity
11B: Appending Odd parity
: Setting is fixed in the CSI master transmission mode,
RXEmn
CCSmn
14
14
14
14
0
0
0
DAPmn
13
13
13
13
0
0
0
Baud rate setting
μ
μ
μ
μ
MCK
CKPmn
PD78F1010, 78F1011, 78F1012):
PD78F1027, 78F1028):
PD78F1013, 78F1014):
PD78F1029, 78F1030):
12
12
) of channel n
12
12
0
0
0
11
11
11
11
0
0
0
EOCmn
10
10
10
10
0
0
0
(UART0 to UART4) (1/2)
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
PTCmn1
0/1
9
9
0
0
9
9
PTCmn0
STSmn
0/1
8
8
0
8
0
8
0
0: Forward (normal) transmission
DIRmn
0/1
0
7
7
7
7
0
SISmn0
1: Reverse transmission
0
6
0
6
0
6
6
mn = 00, 02, q = 0, 1
mn = 00, 02, 10, 12, 20, q = 0 to 4
mn = 00, 02, 10, 12, q = 0 to 3
mn = 00, 02, 10, 12, 20, q = 0 to 4
mn = 00, 02, 10, 12, q = 0 to 3
SLCmn1
: Setting disabled (set to the initial value)
0/1
5
5
1
5
5
0
CHAPTER 14 SERIAL ARRAY UNIT
Transmit data setting
SLCmn0
0/1
TXDq
0
4
4
4
4
0
Interrupt source of channel n
Setting of stop bit
01B: Appending 1 bit
10B: Appending 2 bits
0
0
3
3
0
3
3
1: Buffer empty interrupt
0: Transfer end interrupt
DLSmn2
MDmn2
SOLm2
0/1
2
0
2
1
2
2
Note
MDmn1
DLSmn1
0/1
1
1
1
1
1
0
MDmn0
DLSmn0
SOLm0
0/1
0/1
0/1
0
0
0
0
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