UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 156

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
4.2.2 General-purpose registers
purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
BC, DE, and HL).
names (R0 to R7 and RP0 to RP3).
register bank configuration, an efficient program can be created by switching between a register for normal processing and
a register for interrupts for each bank.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The general-
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX,
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4-
Cautions 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
2. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack
instructions or as a stack area.
memory. Furthermore, the areas of FF300H to FF6FFH and FDF00H to FE2FFH also cannot be
used with the
78F1029, and 78F1030, respectively.
SP←SP−2
SP←SP−4
SP
SP−2
SP−1
SP
SP−4
SP−3
SP−2
SP−1
→
→
↑
↑
↑
↑
↑
↑
↑
↑
CALL, CALLT instructions
μ
PD78F1003, 78F1006 and 78F1009, and
PUSH rp instruction
Register pair higher
Figure 4-23. Data to Be Saved to Stack Memory
Register pair lower
PC19 to PC16
(4-byte stack)
PC15 to PC8
PC7 to PC0
00H
SP←SP−2
SP←SP−4
SP
SP−2
SP−1
SP
SP−4
SP−3
SP−2
SP−1
→
↑
↑
↑
→
↑
↑
↑
↑
↑
μ
Interrupt, BRK instruction
PUSH PSW instruction
PD78F1012, 78F1014, 78F1027, 78F1028,
CHAPTER 4 CPU ARCHITECTURE
PC19 to PC16
(4-byte stack)
PC15 to PC8
PC7 to PC0
PSW
PSW
00H
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