UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 587

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Figure 14-2 shows the block diagram of the serial array unit 1.
Note In the 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L, UART0 (unit 0, channels 0 and 1) is used for LIN-bus
communication.
Serial clock I/O pin
(when CSI20: SCK20)
(when IIC20: SCL20)
Serial data input pin
(when UART3: RxD3)
Serial data input pin
(when CSI20: SI20)
(when IIC20: SDA20)
(when UART2: RxD2)
When UART2
When UART3
Figure 14-2. Block Diagram of Serial Array Unit 1 (78K0R/KF3-L, 78K0R/KG3-L only)
Peripheral enable
register 0 (PER0)
f
CLK
SAU1EN
SNFEN20
elimination
Channel 0
Channel 2 (LIN-bus supported)
Channel 3 (LIN-bus supported)
enabled/
disabled
SNFEN30
Channel 1
TXE
elimination
Noise
10
enabled/
disabled
Noise
PM142
RXE
10
PRS
113
detection
Edge
DAP
Edge/level
Edge/level
Edge/level
10
PRS
112
detection
detection
detection
Serial clock select register 1 (SPS1)
Serial communication operation setting register 10 (SCR10)
CK11
4
Edge/level
0
detection
Output latch
CK11
Selector
CK11
CK11
CKP
(P142)
PRS
10
111
f
SCK
0
f
CLK
EOC
10
CK10
PRS
/2
110
Prescaler
0
to f
0
CK10
CK10
CK10
CLK
CKS10
PTC
101
PRS
103
/2
Serial mode register 10 (SMR10)
Note
Note
f
11
MCK
0
CCS10 STS10 MD102
Selector
PTC
100
PRS
102
(Clock division setting block)
4
1
f
f
CLK
CLK
DIR
10
PRS
101
/2
/2
0
11
1
to
SLC
101
PRS
100
Serial data register 10 (SDR10)
Serial output register 1 (SO1)
1
MD101
SLC
100
f
CKO10
TCLK
DLS
102
(Buffer register block)
0
DLS
101
Shift register
Communication controller
Communication controller
Communication controller
Communication controller
0
(for transmission)
(for transmission)
DLS
100
Mode selection
Mode selection
Mode selection
CSI20 or IIC20
Mode selection
(for reception)
(for reception)
or UART2
0
UART3
UART3
UART2
TSF
0
10
Serial status register 10 (SSR10)
CHAPTER 14 SERIAL ARRAY UNIT
SE13 SE12 SE11
SS13 SS12 SS11
ST13
BFF
0
1
10
0
Serial flag clear trigger
register 10 (SIR10)
SOL12
SOE12
(P144 or P143)
SO11
ST12 ST11
Output latch
FECT
FEF
10
10
Error controller
Error controller
Error controller
controller
PECT
controller
Interrupt
PEF
1
0
0
Output
10
10
SOL10
SOE10
PM144 or PM143
SO10
SE10
SS10
ST10
OVCT
OVF
10
10
information
Clear
Error
Serial channel enable
status register 1 (SE1)
Serial channel stop
register 1 (ST1)
Serial output level
register 1 (SOL1)
Serial channel start
register 1 (SS1)
Serial output enable
register 1 (SOE1)
Noise filter enable
register 0 (NFEN0)
SNFEN
30
Serial transfer end interrupt
(when CSI20: INTCSI20)
(when IIC20: INTIIC20)
(when UART2: INTST2)
Serial transfer end interrupt
(when UART2: INTSR2)
Serial transfer error interrupt
(INTSRE2)
Serial transfer end interrupt
(when UART3: INTSR3)
Serial transfer error interrupt
(INTSRE3)
Serial data output pin
(when CSI20: SO20)
(when IIC20: SDA20)
(when UART2: TxD2)
Serial transfer end interrupt
(when UART3: INTST3)
Serial data output pin
(when UART3: T
SNFEN
20
X
D3)
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