UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 1156

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
B.2 Revision History of Preceding Editions
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Previous
version
(U19291E)
2nd edition
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
Edition
Change of 64-pin plastic FBGA (5 × 5) in 1.4.3 78K0R/KE3-L
Change of description in 2.2.14 RESET
Deletion of description in 2.2.15 REGC
Addition of description to 3.1.2 Mirror area
Change of Table 3-6. Extended SFR (2nd SFR) List (3/4), (4/4)
Change of Figure 4-19. Block Diagram of P80
Change of Figure 4-20. Block Diagram of P81 and P83
Change of Figure 4-21. Block Diagram of P82
Addition of Cautions 1 and 3 in Figure 5-7. Format of 20 MHz Internal High-Speed
Oscillation Control Register (DSCCTL)
Change of Cautions 4 and 5 in Figure 5-9. Format of Operation Speed Mode
Control Register (OSMC)
Change of (3) CPU operating with subsystem clock (D) after reset release (A) in
Table 5-4
Change of (9) CPU clock changing from high-speed system clock (C) to
subsystem clock (D) in Table 5-4
Change of (11) CPU clock changing from subsystem clock (D) to high-speed
system clock (C) in Table 5-4
Change of (12) CPU clock changing from 20 MHz internal high-speed oscillation
clock (J) to internal high-speed oscillation clock (B) in Table 5-4
Change of (14) • STOP mode (H) set while CPU is operating with internal high-
speed oscillation clock (B), •STOP mode (I) set while CPU is operating with
high-speed system clock (C) in Table 5-4
Change of Table 5-5. Changing CPU Clock
Change of description of the CCS0n bit in Figure 6-6 Format of Timer Mode
Register 0n (TMR0n)
Change of description in 6.4.3 (1) Changing values set in registers TO0, TOE0,
TOL0, and TOM0 during timer operation
Addition of description to 6.7.1 (1) Interval timer
Change of Figure 6-35 Block Diagram of Operation as Interval Timer/Square
Wave Output
Addition of (2) When f
Set Contents of Registers During Operation as Interval Timer/Square Wave
Output
Change of Figure 6-38 Operation Procedure of Interval Timer/Square Wave
Output Function
Change of description during operation in Figure 6-42 Operation Procedure When
External Event Counter Function Is Used
Change of description during operation in Figure 6-46 Operation Procedure When
Frequency Divider Function Is Used
Change of description during operation in Figure 6-50 Operation Procedure When
Input Pulse Interval Measurement Function Is Used
SUB
/4 is selected as count clock to Figure 6-37. Example of
Description
APPENDIX B REVISION HISTORY
CHAPTER 1 OUTLINE
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 6 TIMER
ARRAY UNIT
Chapter
(1/7)
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