UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 549

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
12.4.3 Setting window open period of watchdog timer
(000C0H). The outline of the window is as follows.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte
• If “ACH” is written to the watchdog timer enable register (WDTE) during the window open period, the watchdog timer
• Even if “ACH” is written to the WDTE register during the window close period, an abnormality is detected and an
Example: If the window open period is 50%
Caution When data is written to the WDTE register for the first time after reset release, the watchdog timer is
The window open period can be set is as follows.
Cautions 1. The watchdog timer continues its operation during self-programming of the flash memory and
is cleared and starts counting again.
internal reset signal is generated.
cleared in any timing regardless of the window open time, as long as the register is written before the
overflow time, and the watchdog timer starts counting again.
2. When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100%
WINDOW1
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
regardless of the values of the WINDOW1 and WINDOW0 bits.
1
0
0
1
Counting
starts
Table 12-4. Setting Window Open Period of Watchdog Timer
Internal reset signal is generated
if "ACH" is written to WDTE.
WINDOW0
Window close period (50%)
0
1
0
1
Setting prohibited
50%
75%
100%
Window Open Period of Watchdog Timer
Counting starts again when
"ACH" is written to WDTE.
Window close period (50%)
CHAPTER 12 WATCHDOG TIMER
Overflow
time
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