UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 929

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
Notes 1.
Remark The special function register (SFR) mounted depend on the product. See 4.2.4 Special function registers
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Serial interface IICA
Multiplier/divider
Key interrupt
Reset function
Low-voltage detector
Regulator
DMA controller
Register
RESF
LVIS
2.
3.
Reset Source
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
These values vary depending on the reset source.
This value varies depending on the reset source and the option byte.
(SFRs) and 4.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
TRAP bit
WDRF bit
INIRF bit
LVIRF bit
Cleared (0)
Cleared (0EH)
RESET Input
Table 21-2. Hardware Statuses After Reset Acknowledgment (3/4)
IICA shift register (IICA)
IICA status register (IICS)
IICA flag register (IICF)
IICA control register 0 (IICCTL0)
IICA control register 1 (IICCTL1)
IICA low-level width setting register (IICWL)
IICA high-level width setting register (IICWH)
Slave address register (SVA)
Multiplication/division data register A (L) (MDAL)
Multiplication/division data register A (H) (MDAH)
Multiplication/division data register B (L) (MDBL)
Multiplication/division data register B (H) (MDBH)
Multiplication/division data register C (L) (MDCL)
Multiplication/division data register C (H) (MDCH)
Multiplication/division control register (MDUC)
Key return mode register (KRM)
Reset control flag register (RESF)
Low-voltage detection register (LVIM)
Low-voltage detection level select register (LVIS)
Regulator mode control register (RMC)
SFR address registers 0, 1 (DSA0, DSA1)
RAM address registers 0L, 0H, 1L, 1H (DRA0L, DRA0H, DRA1L, DRA1H)
Byte count registers 0L, 0H, 1L, 1H (DBC0L, DBC0H, DBC1L, DBC1H)
Mode control registers 0, 1 (DMC0, DMC1)
Operation control registers 0, 1 (DRC0, DRC1)
Cleared (0)
Cleared (0EH)
Reset by POC
Hardware
Set (1)
Held
Held
Held
Cleared (0EH)
Execution of Illegal
Instruction
Reset by
Set (1)
Held
Held
Held
Cleared (0EH)
Reset by WDT
CHAPTER 21 RESET FUNCTION
Set (1)
Held
Held
Held
Cleared (0EH)
Reset by INIRF
00H
00H
00H
00H
00H
FFH
FFH
00H
0000H
0000H
0000H
0000H
0000H
0000H
00H
00H
00H
00H
0EH
00H
00H
00H
00H
00H
00H
Acknowledgment
Status After Reset
Note 2
Note 3
Note 2
Held
Held
Held
Set (1)
Held
Reset by LVI
Note 1
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