UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 639

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
14.5.2 Master reception
Notes 1. 78K0R/KF3-L, 78K0R/KG3-L only.
Remark
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Master reception is that the 78K0R/Kx3-L outputs a transfer clock and receives data from other device.
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Clock phase
Data direction
3-Wire Serial I/O
2. CSI40 and CSI41 are only mounted in the 78K0R/KF3-L (
3. Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
78K0R/KG3-L (
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L (
78K0R/KF3-L (
78K0R/KG3-L (
PD78F1029, 78F1030).
specifications (see CHAPTER 30
78K0R/KE3-L), CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L)).
m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20, 40, 41)
μ
μ
μ
μ
Channel 0 of
SAU0
SCK00, SI00
INTCSI00
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Overrun error detection flag (OVFmn) only
7 or 8 bits
Max. f
Selectable by the DAPmn bit of the SCRmn register
• DAPmn = 0: Data input starts from the start of the operation of the serial clock.
• DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Selectable by the CKPmn bit of the SCRmn register
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
MSB or LSB first
PD78F1010, 78F1011, 78F1012):
PD78F1027, 78F1028):
PD78F1013, 78F1014):
PD78F1029, 78F1030):
CSI00
CLK
/4 [Hz], Min. f
Channel 1 of
SAU0
SCK01, SI01
INTCSI01
CSI01
CLK
/(2 × 2
ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L,
11
× 128) [Hz]
Channel 2 of
SAU0
SCK10, SI10
INTCSI10
CSI10
Note 3
mn = 00 to 02, p = 00, 01, 10
mn = 00 to 02, 10, p = 00, 01, 10, 20
mn = 00 to 02, 10, 20, 21, p = 00, 01, 10, 20, 40, 41
mn = 00 to 02, 10, p = 00, 01, 10, 20
mn = 00 to 02, 10, 20, 21, p = 00, 01, 10, 20, 40, 41
μ
f
CLK
Channel 0 of
SAU1
SCK20, SI20
INTCSI20
PD78F1027, 78F1028) and 78K0R/KG3-L (
CSI20
: System clock frequency
CHAPTER 14 SERIAL ARRAY UNIT
Note 1
Channel 0 of
SAU2
SCK40, SI40
INTCSI40
CSI40
Note 2
Channel 1 of
SAU2
SCK41, SI41
INTCSI41
CSI41
Note 2
639
μ