UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 489

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
TAU
default
setting
Channel
default
setting
(Note and Remark are listed on the next page.)
Figure 8-75. Operation Procedure When Multiple PWM Output Function Is Used (1/3)
Sets the TAU0EN and TAU1EN bits of peripheral enable
registers 0, 2 (PER0, PER2) to 1.
Sets timer clock select register m (TPSm).
Sets timer mode registers mn, mp, mq (TMRmn,
TMRmp, TMRmq) of each channel to be used
(determines operation mode of channels).
An interval (period) value is set to timer data register mn
(TDRmn) of the master channel, and a duty factor is set
to the TDRmp and TDRmq registers of the slave
channels.
Sets slave channels.
Determines clock frequencies of CKm0 and CKm1.
The TOMmp and TOMmq bits of timer output mode
register m (TOMm) are set to 1 (slave channel output
mode).
Clears the TOLmp and TOLmq bits to 0.
Sets the TOmp and TOmq bits and determines default
level of the TOmp and TOmq outputs.
Sets the TOEmp and TOEmq bits to 1 and enables
operation of TOmp and TOmq.
Clears the port register and port mode register to 0.
Software Operation
Note
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOmp and TOmq pins go into Hi-Z output state.
The TOmp and TOmq default setting levels are output
when the port mode register is in output mode and the port
register is 0.
TOmp and TOmq do not change because channels stop
operating.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
CHAPTER 8 TIMER ARRAY UNIT
Hardware Status
489